From 15fa992cc8467b4cbd8ebea62e3e4c947827137e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 17 Jun 2016 10:00:28 +0300 Subject: intel/model_6ex: Prepare for dynamic CONFIG_RAMTOP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15229 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/lenovo/t400/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/lenovo/t400') diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 16676faa02..dbec8d0e90 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -23,13 +23,13 @@ #include #include #include +#include #include #include #include #include #include #include -#include #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) @@ -67,7 +67,7 @@ static void early_lpc_setup(void) pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681); } -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { sysinfo_t sysinfo; int s3resume = 0; -- cgit v1.2.3