From c1dc2d5e687cd8ba8164d593b875977f2f6dcbd4 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 7 Aug 2019 16:50:24 +0200 Subject: mb/lenovo/t60: Switch to override tree Change-Id: I13c0134b22e2203e6cee6ecafda0dae89e086aff Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/34779 Reviewed-by: Arthur Heymans Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/t60/Kconfig | 4 +- src/mainboard/lenovo/t60/devicetree.cb | 229 +++++++++++++++++++ .../lenovo/t60/variants/t60/devicetree.cb | 243 --------------------- .../lenovo/t60/variants/t60/overridetree.cb | 69 ++++++ .../lenovo/t60/variants/z61t/devicetree.cb | 241 -------------------- .../lenovo/t60/variants/z61t/overridetree.cb | 64 ++++++ 6 files changed, 364 insertions(+), 486 deletions(-) create mode 100644 src/mainboard/lenovo/t60/devicetree.cb delete mode 100644 src/mainboard/lenovo/t60/variants/t60/devicetree.cb create mode 100644 src/mainboard/lenovo/t60/variants/t60/overridetree.cb delete mode 100644 src/mainboard/lenovo/t60/variants/z61t/devicetree.cb create mode 100644 src/mainboard/lenovo/t60/variants/z61t/overridetree.cb (limited to 'src/mainboard/lenovo/t60') diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 725528de5b..ad74f63d46 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -33,9 +33,9 @@ config VARIANT_DIR default "t60" if BOARD_LENOVO_T60 default "z61t" if BOARD_LENOVO_Z61T -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb new file mode 100644 index 0000000000..70900eae2c --- /dev/null +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -0,0 +1,229 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + # IGD Displays + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + + register "gpu_hotplug" = "0x00000220" + register "gpu_lvds_use_spread_spectrum_clock" = "1" + register "pwm_freq" = "275" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" + + device cpu_cluster 0 on + chip cpu/intel/socket_m + device lapic 0 on end + end + end + + register "pci_mmio_size" = "768" + + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x2015 + end + device pci 01.0 on # PCI-e + device pci 00.0 on # VGA + subsystemid 0x17aa 0x20a4 + end + end + + device pci 02.0 on # GMA Graphics controller + subsystemid 0x17aa 0x201a + end + device pci 02.1 on # display controller + subsystemid 0x17aa 0x201a + end + + chip southbridge/intel/i82801gx + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi13_routing" = "2" + register "gpi12_routing" = "2" + register "gpi8_routing" = "2" + + register "sata_ports_implemented" = "0x01" + + register "gpe0_en" = "0x11000006" + register "alt_gp_smi_en" = "0x1000" + + register "c4onc3_enable" = "1" + register "c3_latency" = "0x23" + register "docking_supported" = "1" + register "p_cnt_throttling_supported" = "1" + + device pci 1b.0 on # Audio Controller + subsystemid 0x17aa 0x2010 + end + device pci 1c.0 on # Ethernet + subsystemid 0x17aa 0x2001 + end + device pci 1c.1 on end # WLAN + device pci 1c.2 on end # PCIe port 3 + device pci 1c.3 on end # PCIe port 4 + device pci 1c.4 off end # PCIe port 5 + device pci 1c.5 off end # PCIe port 6 + + device pci 1d.0 on # USB UHCI + subsystemid 0x17aa 0x200a + end + device pci 1d.1 on # USB UHCI + subsystemid 0x17aa 0x200a + end + device pci 1d.2 on # USB UHCI + subsystemid 0x17aa 0x200a + end + device pci 1d.3 on # USB UHCI + subsystemid 0x17aa 0x200a + end + device pci 1d.7 on # USB2 EHCI + subsystemid 0x17aa 0x200b + end + device pci 1e.0 on # PCI Bridge + chip southbridge/ti/pci1x2x + device pci 00.0 on + subsystemid 0x17aa 0x2012 + end + register "scr" = "0x0844d070" + register "mrr" = "0x01d01002" + end + end + device pci 1e.2 off end # AC'97 Audio + device pci 1e.3 off end # AC'97 Modem + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x17aa 0x2009 + chip ec/lenovo/pmh7 + device pnp ff.1 on # dummy + end + + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa6" + register "config1" = "0x05" + register "config2" = "0xa0" + register "config3" = "0x01" + + register "beepmask0" = "0xfe" + register "beepmask1" = "0x96" + register "has_power_management_beeps" = "1" + + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xf4" + register "event5_enable" = "0x3f" + register "event6_enable" = "0x80" + register "event7_enable" = "0x01" + register "event8_enable" = "0x01" + register "event9_enable" = "0xff" + register "eventa_enable" = "0xff" + register "eventb_enable" = "0xff" + register "eventc_enable" = "0x3c" + register "eventd_enable" = "0xff" + end + chip superio/nsc/pc87382 + device pnp 164e.2 on # IR + io 0x60 = 0x2f8 + end + + device pnp 164e.3 off # Serial Port + io 0x60 = 0x3f8 + end + + device pnp 164e.7 on # GPIO + io 0x60 = 0x1680 + end + + device pnp 164e.19 on # DLPC + io 0x60 = 0x164c + end + end + + chip superio/nsc/pc87384 + device pnp 2e.0 off #FDC + end + + device pnp 2e.1 on # Parallel Port + io 0x60 = 0x3bc + irq 0x70 = 7 + end + + device pnp 2e.2 off # Serial Port / IR + io 0x60 = 0x2f8 + irq 0x70 = 4 + end + + device pnp 2e.3 on # Serial Port + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + + device pnp 2e.7 on # GPIO + io 0x60 = 0x1620 + end + + device pnp 2e.a off # WDT + end + end + end + device pci 1f.2 on # SATA + subsystemid 0x17aa 0x200d + end + device pci 1f.3 on # SMBUS + subsystemid 0x17aa 0x200f + chip drivers/i2c/ck505 + device i2c 69 on end + end + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end + end + end +end diff --git a/src/mainboard/lenovo/t60/variants/t60/devicetree.cb b/src/mainboard/lenovo/t60/variants/t60/devicetree.cb deleted file mode 100644 index 9279dcb01a..0000000000 --- a/src/mainboard/lenovo/t60/variants/t60/devicetree.cb +++ /dev/null @@ -1,243 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2011 Sven Schnelle -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/i945 - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - register "gpu_hotplug" = "0x00000220" - register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "pwm_freq" = "275" - register "gpu_panel_power_up_delay" = "250" - register "gpu_panel_power_backlight_on_delay" = "2380" - register "gpu_panel_power_down_delay" = "250" - register "gpu_panel_power_backlight_off_delay" = "2380" - register "gpu_panel_power_cycle_delay" = "2" - - device cpu_cluster 0 on - chip cpu/intel/socket_m - device lapic 0 on end - end - end - - register "pci_mmio_size" = "768" - - device domain 0 on - device pci 00.0 on # Host bridge - subsystemid 0x17aa 0x2015 - end - device pci 01.0 on # PCI-e - device pci 00.0 on # VGA - subsystemid 0x17aa 0x20a4 - end - end - - device pci 02.0 on # GMA Graphics controller - subsystemid 0x17aa 0x201a - end - device pci 02.1 on # display controller - subsystemid 0x17aa 0x201a - end - - chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi13_routing" = "2" - register "gpi12_routing" = "2" - register "gpi8_routing" = "2" - - register "sata_ports_implemented" = "0x01" - - register "gpe0_en" = "0x11000006" - register "alt_gp_smi_en" = "0x1000" - - register "c4onc3_enable" = "1" - register "c3_latency" = "0x23" - register "docking_supported" = "1" - register "p_cnt_throttling_supported" = "1" - - device pci 1b.0 on # Audio Controller - subsystemid 0x17aa 0x2010 - end - device pci 1c.0 on # Ethernet - subsystemid 0x17aa 0x2001 - end - device pci 1c.1 on end # WLAN - device pci 1c.2 on end # PCIe port 3 - device pci 1c.3 on end # PCIe port 4 - device pci 1c.4 off end # PCIe port 5 - device pci 1c.5 off end # PCIe port 6 - - device pci 1d.0 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.1 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.2 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.3 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.7 on # USB2 EHCI - subsystemid 0x17aa 0x200b - end - device pci 1e.0 on # PCI Bridge - chip southbridge/ti/pci1x2x - device pci 00.0 on - subsystemid 0x17aa 0x2012 - end - register "scr" = "0x0844d070" - register "mrr" = "0x01d01002" - - end - end - device pci 1e.2 off end # AC'97 Audio - device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # PCI-LPC bridge - subsystemid 0x17aa 0x2009 - chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end - - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa6" - register "config1" = "0x05" - register "config2" = "0xa0" - register "config3" = "0x01" - - register "beepmask0" = "0xfe" - register "beepmask1" = "0x96" - register "has_power_management_beeps" = "1" - - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xf4" - register "event5_enable" = "0x3f" - register "event6_enable" = "0x80" - register "event7_enable" = "0x01" - register "event8_enable" = "0x01" - register "event9_enable" = "0xff" - register "eventa_enable" = "0xff" - register "eventb_enable" = "0xff" - register "eventc_enable" = "0x3c" - register "eventd_enable" = "0xff" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "7" - register "bdc_gpio_lvl" = "0" - end - chip superio/nsc/pc87382 - device pnp 164e.2 on # IR - io 0x60 = 0x2f8 - end - - device pnp 164e.3 off # Serial Port - io 0x60 = 0x3f8 - end - - device pnp 164e.7 on # GPIO - io 0x60 = 0x1680 - end - - device pnp 164e.19 on # DLPC - io 0x60 = 0x164c - end - end - - chip superio/nsc/pc87384 - device pnp 2e.0 off #FDC - end - - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x3bc - irq 0x70 = 7 - end - - device pnp 2e.2 off # Serial Port / IR - io 0x60 = 0x2f8 - irq 0x70 = 4 - end - - device pnp 2e.3 on # Serial Port - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - - device pnp 2e.7 on # GPIO - io 0x60 = 0x1620 - end - - device pnp 2e.a off # WDT - end - end - end - device pci 1f.1 on # IDE - subsystemid 0x17aa 0x200c - end - device pci 1f.2 on # SATA - subsystemid 0x17aa 0x200d - end - device pci 1f.3 on # SMBUS - subsystemid 0x17aa 0x200f - chip drivers/i2c/ck505 - register "mask" = "{ 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff }" - register "regs" = "{ 0x2e, 0xf7, 0x3c, - 0x20, 0x01, 0x00, 0x1b, 0x01, - 0x54, 0xff, 0xff, 0x07 }" - device i2c 69 on end - end - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end - end - end -end diff --git a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb new file mode 100644 index 0000000000..eee3a4d575 --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb @@ -0,0 +1,69 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x2015 + end + device pci 01.0 on # PCI-e + device pci 00.0 on # VGA + subsystemid 0x17aa 0x20a4 + end + end + chip southbridge/intel/i82801gx + device pci 1c.0 on # Ethernet + subsystemid 0x17aa 0x2001 + end + device pci 1c.1 on end # WLAN + device pci 1c.2 on end # PCIe port 3 + device pci 1c.3 on end # PCIe port 4 + device pci 1e.0 on # PCI Bridge + chip southbridge/ti/pci1x2x + device pci 00.0 on + subsystemid 0x17aa 0x2012 + end + end + end + device pci 1f.0 on # PCI-LPC bridge + chip ec/lenovo/h8 + register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "7" + register "bdc_gpio_lvl" = "0" + end + chip superio/nsc/pc87384 + device pnp 2e.2 off # Serial Port / IR + irq 0x70 = 4 + end + end + end + device pci 1f.1 on # IDE + subsystemid 0x17aa 0x200c + end + device pci 1f.3 on # SMBUS + chip drivers/i2c/ck505 + register "mask" = "{ 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }" + register "regs" = "{ 0x2e, 0xf7, 0x3c, + 0x20, 0x01, 0x00, 0x1b, 0x01, + 0x54, 0xff, 0xff, 0x07 }" + end + end + end + end +end diff --git a/src/mainboard/lenovo/t60/variants/z61t/devicetree.cb b/src/mainboard/lenovo/t60/variants/z61t/devicetree.cb deleted file mode 100644 index d35c62b09c..0000000000 --- a/src/mainboard/lenovo/t60/variants/z61t/devicetree.cb +++ /dev/null @@ -1,241 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2011 Sven Schnelle -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/i945 - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - register "gpu_hotplug" = "0x00000220" - register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "pwm_freq" = "275" - register "gpu_panel_power_up_delay" = "250" - register "gpu_panel_power_backlight_on_delay" = "2380" - register "gpu_panel_power_down_delay" = "250" - register "gpu_panel_power_backlight_off_delay" = "2380" - register "gpu_panel_power_cycle_delay" = "2" - - device cpu_cluster 0 on - chip cpu/intel/socket_m - device lapic 0 on end - end - end - - register "pci_mmio_size" = "768" - - device domain 0 on - device pci 00.0 on # Host bridge - subsystemid 0x17aa 0x2017 - end - - device pci 01.0 on # PEG - device pci 00.0 on end # VGA - end - - device pci 02.0 on # GMA Graphics controller - subsystemid 0x17aa 0x201a - end - device pci 02.1 on # display controller - subsystemid 0x17aa 0x201a - end - - chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi13_routing" = "2" - register "gpi12_routing" = "2" - register "gpi8_routing" = "2" - - register "sata_ports_implemented" = "0x01" - - register "gpe0_en" = "0x11000006" - register "alt_gp_smi_en" = "0x1000" - - register "c4onc3_enable" = "1" - register "c3_latency" = "0x23" - register "docking_supported" = "1" - register "p_cnt_throttling_supported" = "1" - - device pci 1b.0 on # Audio Controller - subsystemid 0x17aa 0x2010 - end - device pci 1c.0 on # PCI Express Port 1 - subsystemid 0x17aa 0x2011 - end - device pci 1c.1 on # PCI Express Port 2 - subsystemid 0x17aa 0x2011 - end - device pci 1c.2 on # PCI Express Port 3 - subsystemid 0x17aa 0x2011 - end - device pci 1c.3 on # PCI Express Port 4 - subsystemid 0x17aa 0x2011 - end - device pci 1c.4 off end # PCIe port 5 - device pci 1c.5 off end # PCIe port 6 - - device pci 1d.0 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.1 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.2 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.3 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.7 on # USB2 EHCI - subsystemid 0x17aa 0x200b - end - device pci 1e.0 on # PCI Bridge - chip southbridge/ti/pci1x2x - device pci 00.0 on - subsystemid 0x17aa 0x2013 - end - register "scr" = "0x0844d070" - register "mrr" = "0x01d01002" - - end - end - device pci 1e.2 off end # AC'97 Audio - device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # PCI-LPC bridge - subsystemid 0x17aa 0x2009 - chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end - - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa6" - register "config1" = "0x05" - register "config2" = "0xa0" - register "config3" = "0x01" - - register "beepmask0" = "0xfe" - register "beepmask1" = "0x96" - register "has_power_management_beeps" = "1" - - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xf4" - register "event5_enable" = "0x3f" - register "event6_enable" = "0x80" - register "event7_enable" = "0x01" - register "event8_enable" = "0x01" - register "event9_enable" = "0xff" - register "eventa_enable" = "0xff" - register "eventb_enable" = "0xff" - register "eventc_enable" = "0x3c" - register "eventd_enable" = "0xff" - - end - chip superio/nsc/pc87382 - device pnp 164e.2 on # IR - io 0x60 = 0x2f8 - end - - device pnp 164e.3 off # Serial Port - io 0x60 = 0x3f8 - end - - device pnp 164e.7 on # GPIO - io 0x60 = 0x1680 - end - - device pnp 164e.19 on # DLPC - io 0x60 = 0x164c - end - end - - chip superio/nsc/pc87384 - device pnp 2e.0 off #FDC - end - - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x3bc - irq 0x70 = 7 - end - - device pnp 2e.2 off # Serial Port / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - - device pnp 2e.3 on # Serial Port - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - - device pnp 2e.7 on # GPIO - io 0x60 = 0x1620 - end - - device pnp 2e.a off # WDT - end - end - end - device pci 1f.2 on # SATA - subsystemid 0x17aa 0x200d - end - device pci 1f.3 on # SMBUS - subsystemid 0x17aa 0x200f - chip drivers/i2c/ck505 - register "mask" = "{ 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff }" - # vendor clockgen setup - register "regs" = "{ 0x6d, 0xff, 0xff, - 0x20, 0x41, 0x7f, 0x18, 0x00 }" - device i2c 69 on end - end - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end - end - end -end diff --git a/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb new file mode 100644 index 0000000000..d29df3b488 --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x2017 + end + device pci 01.0 on # PEG + device pci 00.0 on end # VGA + end + chip southbridge/intel/i82801gx + device pci 1c.0 on # PCI Express Port 1 + subsystemid 0x17aa 0x2011 + end + device pci 1c.1 on # PCI Express Port 2 + subsystemid 0x17aa 0x2011 + end + device pci 1c.2 on # PCI Express Port 3 + subsystemid 0x17aa 0x2011 + end + device pci 1c.3 on # PCI Express Port 4 + subsystemid 0x17aa 0x2011 + end + device pci 1e.0 on # PCI Bridge + chip southbridge/ti/pci1x2x + device pci 00.0 on + subsystemid 0x17aa 0x2013 + end + end + end + device pci 1f.0 on # PCI-LPC bridge + chip superio/nsc/pc87384 + device pnp 2e.2 off # Serial Port / IR + irq 0x70 = 3 + end + end + end + device pci 1f.3 on # SMBUS + chip drivers/i2c/ck505 + register "mask" = "{ 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff }" + # vendor clockgen setup + register "regs" = "{ 0x6d, 0xff, 0xff, + 0x20, 0x41, 0x7f, 0x18, 0x00 }" + end + end + end + end +end -- cgit v1.2.3