From fa5d0f835b1f3bb8907e616913cbf7b91d09ef26 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 19:11:50 +0100 Subject: nb/intel/sandybridge: Set up console in bootblock Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc | 2 + src/mainboard/lenovo/x1_carbon_gen1/early_init.c | 101 ++++++++++++++++++++++ src/mainboard/lenovo/x1_carbon_gen1/romstage.c | 105 ----------------------- 3 files changed, 103 insertions(+), 105 deletions(-) create mode 100644 src/mainboard/lenovo/x1_carbon_gen1/early_init.c delete mode 100644 src/mainboard/lenovo/x1_carbon_gen1/romstage.c (limited to 'src/mainboard/lenovo/x1_carbon_gen1') diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc index 8ce77fc77d..f6331a61d1 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc @@ -20,3 +20,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c new file mode 100644 index 0000000000..c70b21d36b --- /dev/null +++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2017 Alexander Couzens + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void mainboard_pch_lpc_setup(void) +{ + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled, current, OC pin */ + { 0, 3, 0 }, /* P00 disconnected */ + { 1, 1, 1 }, /* P01 left or right */ + { 0, 1, 3 }, /* P02 disconnected */ + { 1, 3, -1 },/* P03 WWAN */ + { 0, 1, 2 }, /* P04 disconnected */ + { 0, 1, -1 },/* P05 disconnected */ + { 0, 1, -1 },/* P06 disconnected */ + { 0, 2, -1 },/* P07 disconnected */ + { 0, 1, -1 },/* P08 disconnected */ + { 1, 2, 5 }, /* P09 left or right */ + { 1, 3, -1 },/* P10 FPR */ + { 1, 3, -1 },/* P11 Bluetooth */ + { 1, 1, -1 },/* P12 WLAN */ + { 1, 1, -1 },/* P13 Camera */ +}; + +static uint8_t *get_spd_data(int spd_index) +{ + uint8_t *spd_file; + size_t spd_file_len; + + printk(BIOS_DEBUG, "spd index %d\n", spd_index); + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < spd_index * 256) + die("Missing SPD data."); + + return spd_file + spd_index * 256; +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + uint8_t *memory; + const int spd_gpio_vector[] = {25, 45, -1}; + int spd_index = get_gpios(spd_gpio_vector); + + /* 4gb model = 0, 8gb model = 1 */ + /* int extended_memory_version = get_gpio(44); */ + + /* + * So far there is no need to parse gpio 44, as the 4GiB use + * the hynix or elpida memory and 8 GiB versions use samsung. + * All version use both channels. + * But we might miss some versions. + */ + + /* + * GPIO45 GPIO25 + * 0 0 elpida + * 0 1 hynix + * 1 0 samsung + * 1 1 reserved + */ + + if (spd_index == 3) + die("Unsupported Memory. (detected 'reserved' memory configuration)."); + + memory = get_spd_data(spd_index); + memcpy(&spd[0], memory, 256); + memcpy(&spd[2], memory, 256); +} diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c deleted file mode 100644 index 1f027ffab8..0000000000 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2017 Alexander Couzens - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled, current, OC pin */ - { 0, 3, 0 }, /* P00 disconnected */ - { 1, 1, 1 }, /* P01 left or right */ - { 0, 1, 3 }, /* P02 disconnected */ - { 1, 3, -1 },/* P03 WWAN */ - { 0, 1, 2 }, /* P04 disconnected */ - { 0, 1, -1 },/* P05 disconnected */ - { 0, 1, -1 },/* P06 disconnected */ - { 0, 2, -1 },/* P07 disconnected */ - { 0, 1, -1 },/* P08 disconnected */ - { 1, 2, 5 }, /* P09 left or right */ - { 1, 3, -1 },/* P10 FPR */ - { 1, 3, -1 },/* P11 Bluetooth */ - { 1, 1, -1 },/* P12 WLAN */ - { 1, 1, -1 },/* P13 Camera */ -}; - -static uint8_t *get_spd_data(int spd_index) -{ - uint8_t *spd_file; - size_t spd_file_len; - - printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < spd_index * 256) - die("Missing SPD data."); - - return spd_file + spd_index * 256; -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - uint8_t *memory; - const int spd_gpio_vector[] = {25, 45, -1}; - int spd_index = get_gpios(spd_gpio_vector); - - /* 4gb model = 0, 8gb model = 1 */ - /* int extended_memory_version = get_gpio(44); */ - - /* - * So far there is no need to parse gpio 44, as the 4GiB use - * the hynix or elpida memory and 8 GiB versions use samsung. - * All version use both channels. - * But we might miss some versions. - */ - - /* - * GPIO45 GPIO25 - * 0 0 elpida - * 0 1 hynix - * 1 0 samsung - * 1 1 reserved - */ - - if (spd_index == 3) - die("Unsupported Memory. (detected 'reserved' memory configuration)."); - - memory = get_spd_data(spd_index); - memcpy(&spd[0], memory, 256); - memcpy(&spd[2], memory, 256); -} - -void mainboard_config_superio(void) -{ -} -- cgit v1.2.3