From c70eed1e6202c928803f3e7f79161cd247a62b23 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 22 May 2018 02:18:00 +0300 Subject: device: Use pcidev_on_root() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) Reviewed-by: Piotr Król Reviewed-by: Arthur Heymans --- src/mainboard/lenovo/x201/mainboard.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard/lenovo/x201/mainboard.c') diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 419f8177a2..182d041f73 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -82,7 +82,7 @@ static void mainboard_enable(struct device *dev) dev->ops->init = mainboard_init; dev->ops->acpi_fill_ssdt_generator = fill_ssdt; - pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + pmbase = pci_read_config32(pcidev_on_root(0x1f, 0), PMBASE) & 0xff80; printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); @@ -90,9 +90,9 @@ static void mainboard_enable(struct device *dev) outl(0, pmbase + SMI_EN); enable_lapic(); - pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE, + pci_write_config32(pcidev_on_root(0x1f, 0), GPIO_BASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL, + pci_write_config8(pcidev_on_root(0x1f, 0), GPIO_CNTL, 0x10); /* If we're resuming from suspend, blink suspend LED */ -- cgit v1.2.3