From fa5d0f835b1f3bb8907e616913cbf7b91d09ef26 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 19:11:50 +0100 Subject: nb/intel/sandybridge: Set up console in bootblock Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/lenovo/l520/Makefile.inc | 3 +- src/mainboard/lenovo/l520/early_init.c | 46 ++++++++++ src/mainboard/lenovo/l520/romstage.c | 50 ----------- src/mainboard/lenovo/s230u/Makefile.inc | 2 + src/mainboard/lenovo/s230u/early_init.c | 102 ++++++++++++++++++++++ src/mainboard/lenovo/s230u/romstage.c | 106 ----------------------- src/mainboard/lenovo/t420/Makefile.inc | 2 + src/mainboard/lenovo/t420/early_init.c | 84 ++++++++++++++++++ src/mainboard/lenovo/t420/romstage.c | 88 ------------------- src/mainboard/lenovo/t420s/Makefile.inc | 2 + src/mainboard/lenovo/t420s/early_init.c | 83 ++++++++++++++++++ src/mainboard/lenovo/t420s/romstage.c | 87 ------------------- src/mainboard/lenovo/t430/Makefile.inc | 3 +- src/mainboard/lenovo/t430/early_init.c | 79 +++++++++++++++++ src/mainboard/lenovo/t430/romstage.c | 83 ------------------ src/mainboard/lenovo/t430s/Makefile.inc | 2 + src/mainboard/lenovo/t430s/early_init.c | 25 ++++++ src/mainboard/lenovo/t430s/romstage.c | 29 ------- src/mainboard/lenovo/t520/Makefile.inc | 2 + src/mainboard/lenovo/t520/early_init.c | 79 +++++++++++++++++ src/mainboard/lenovo/t520/romstage.c | 83 ------------------ src/mainboard/lenovo/t530/Makefile.inc | 2 + src/mainboard/lenovo/t530/early_init.c | 62 +++++++++++++ src/mainboard/lenovo/t530/romstage.c | 66 -------------- src/mainboard/lenovo/x131e/Makefile.inc | 2 + src/mainboard/lenovo/x131e/early_init.c | 44 ++++++++++ src/mainboard/lenovo/x131e/romstage.c | 48 ---------- src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc | 2 + src/mainboard/lenovo/x1_carbon_gen1/early_init.c | 101 +++++++++++++++++++++ src/mainboard/lenovo/x1_carbon_gen1/romstage.c | 105 ---------------------- src/mainboard/lenovo/x220/Makefile.inc | 2 + src/mainboard/lenovo/x220/early_init.c | 93 ++++++++++++++++++++ src/mainboard/lenovo/x220/romstage.c | 97 --------------------- src/mainboard/lenovo/x230/Makefile.inc | 2 + src/mainboard/lenovo/x230/early_init.c | 53 ++++++++++++ src/mainboard/lenovo/x230/romstage.c | 57 ------------ 36 files changed, 875 insertions(+), 901 deletions(-) create mode 100644 src/mainboard/lenovo/l520/early_init.c delete mode 100644 src/mainboard/lenovo/l520/romstage.c create mode 100644 src/mainboard/lenovo/s230u/early_init.c delete mode 100644 src/mainboard/lenovo/s230u/romstage.c create mode 100644 src/mainboard/lenovo/t420/early_init.c delete mode 100644 src/mainboard/lenovo/t420/romstage.c create mode 100644 src/mainboard/lenovo/t420s/early_init.c delete mode 100644 src/mainboard/lenovo/t420s/romstage.c create mode 100644 src/mainboard/lenovo/t430/early_init.c delete mode 100644 src/mainboard/lenovo/t430/romstage.c create mode 100644 src/mainboard/lenovo/t430s/early_init.c delete mode 100644 src/mainboard/lenovo/t430s/romstage.c create mode 100644 src/mainboard/lenovo/t520/early_init.c delete mode 100644 src/mainboard/lenovo/t520/romstage.c create mode 100644 src/mainboard/lenovo/t530/early_init.c delete mode 100644 src/mainboard/lenovo/t530/romstage.c create mode 100644 src/mainboard/lenovo/x131e/early_init.c delete mode 100644 src/mainboard/lenovo/x131e/romstage.c create mode 100644 src/mainboard/lenovo/x1_carbon_gen1/early_init.c delete mode 100644 src/mainboard/lenovo/x1_carbon_gen1/romstage.c create mode 100644 src/mainboard/lenovo/x220/early_init.c delete mode 100644 src/mainboard/lenovo/x220/romstage.c create mode 100644 src/mainboard/lenovo/x230/early_init.c delete mode 100644 src/mainboard/lenovo/x230/romstage.c (limited to 'src/mainboard/lenovo') diff --git a/src/mainboard/lenovo/l520/Makefile.inc b/src/mainboard/lenovo/l520/Makefile.inc index 14cd059011..c03276795c 100644 --- a/src/mainboard/lenovo/l520/Makefile.inc +++ b/src/mainboard/lenovo/l520/Makefile.inc @@ -13,9 +13,10 @@ ## GNU General Public License for more details. ## -romstage-y += romstage.c bootblock-y += gpio.c romstage-y += gpio.c smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/l520/early_init.c b/src/mainboard/lenovo/l520/early_init.c new file mode 100644 index 0000000000..d63a667737 --- /dev/null +++ b/src/mainboard/lenovo/l520/early_init.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c deleted file mode 100644 index af73537f24..0000000000 --- a/src/mainboard/lenovo/l520/romstage.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2016 Patrick Rudolph - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 0, -1 }, -}; - -void mainboard_config_superio(void) -{ -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} diff --git a/src/mainboard/lenovo/s230u/Makefile.inc b/src/mainboard/lenovo/s230u/Makefile.inc index aa4c4f879d..12e77097e4 100644 --- a/src/mainboard/lenovo/s230u/Makefile.inc +++ b/src/mainboard/lenovo/s230u/Makefile.inc @@ -16,3 +16,5 @@ SPD_SOURCES += samsung_2gb # 0b0111 SPD_SOURCES += hynix_2gb # 0b1000 ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c new file mode 100644 index 0000000000..6bc92b2cac --- /dev/null +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tobias Diedrich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ec.h" + +#define SPD_LEN 256 + +void mainboard_pch_lpc_setup(void) +{ + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); + + /* Memory map KB9012 EC registers */ + pci_write_config32( + PCH_LPC_DEV, LGMR, + CONFIG_EC_BASE_ADDRESS | 1); + pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0); + + /* Enable external USB port power. */ + if (CONFIG(USBDEBUG)) + ec_mm_set_bit(0x3b, 4); +} + +void mainboard_late_rcba_config(void) +{ + /* Disable devices. */ + RCBA32(BUC) = 0x00000020; +} +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 0, 0 }, + { 1, 1, 1 }, + { 1, 0, 1 }, + { 1, 1, 2 }, + { 1, 0, 2 }, + { 0, 0, 3 }, + { 0, 1, 3 }, + { 1, 0, 4 }, + { 1, 1, 4 }, + { 1, 1, 5 }, + { 1, 1, 5 }, + { 1, 1, 6 }, + { 1, 1, 6 }, +}; + +static const char *mainboard_spd_names[9] = { + "ELPIDA 4GB", + "SAMSUNG 4GB", + "HYNIX 4GB", + "ELPIDA 8GB", + "SAMSUNG 8GB", + "HYNIX 8GB", + "ELPIDA 2GB", + "SAMSUNG 2GB", + "HYNIX 2GB", +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + void *spd_file; + size_t spd_file_len = 0; + const int spd_gpios[] = {71, 70, 16, 48, -1}; + + u32 spd_index = get_gpios(spd_gpios); + if (spd_index >= ARRAY_SIZE(mainboard_spd_names)) { + /* Fallback to pessimistic 2GB image (ELPIDA 2GB) */ + spd_index = 6; + } + + printk(BIOS_INFO, "SPD index %d (%s)\n", + spd_index, mainboard_spd_names[spd_index]); + + /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + + if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN) + die("SPD data not found."); + + memcpy(spd, spd_file + SPD_LEN * spd_index, SPD_LEN); +} diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c deleted file mode 100644 index 0552170668..0000000000 --- a/src/mainboard/lenovo/s230u/romstage.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Tobias Diedrich - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "ec.h" - -#define SPD_LEN 256 - -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); - - /* Memory map KB9012 EC registers */ - pci_write_config32( - PCH_LPC_DEV, LGMR, - CONFIG_EC_BASE_ADDRESS | 1); - pci_write_config16(PCH_LPC_DEV, BIOS_DEC_EN1, 0xffc0); - - /* Enable external USB port power. */ - if (CONFIG(USBDEBUG)) - ec_mm_set_bit(0x3b, 4); -} - -void mainboard_late_rcba_config(void) -{ - /* Disable devices. */ - RCBA32(BUC) = 0x00000020; -} -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 0, 0 }, - { 1, 1, 1 }, - { 1, 0, 1 }, - { 1, 1, 2 }, - { 1, 0, 2 }, - { 0, 0, 3 }, - { 0, 1, 3 }, - { 1, 0, 4 }, - { 1, 1, 4 }, - { 1, 1, 5 }, - { 1, 1, 5 }, - { 1, 1, 6 }, - { 1, 1, 6 }, -}; - -void mainboard_config_superio(void) -{ -} - -static const char *mainboard_spd_names[9] = { - "ELPIDA 4GB", - "SAMSUNG 4GB", - "HYNIX 4GB", - "ELPIDA 8GB", - "SAMSUNG 8GB", - "HYNIX 8GB", - "ELPIDA 2GB", - "SAMSUNG 2GB", - "HYNIX 2GB", -}; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - void *spd_file; - size_t spd_file_len = 0; - const int spd_gpios[] = {71, 70, 16, 48, -1}; - - u32 spd_index = get_gpios(spd_gpios); - if (spd_index >= ARRAY_SIZE(mainboard_spd_names)) { - /* Fallback to pessimistic 2GB image (ELPIDA 2GB) */ - spd_index = 6; - } - - printk(BIOS_INFO, "SPD index %d (%s)\n", - spd_index, mainboard_spd_names[spd_index]); - - /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - - if (!spd_file || spd_file_len < SPD_LEN * spd_index + SPD_LEN) - die("SPD data not found."); - - memcpy(spd, spd_file + SPD_LEN * spd_index, SPD_LEN); -} diff --git a/src/mainboard/lenovo/t420/Makefile.inc b/src/mainboard/lenovo/t420/Makefile.inc index 3914f51561..080812e44a 100644 --- a/src/mainboard/lenovo/t420/Makefile.inc +++ b/src/mainboard/lenovo/t420/Makefile.inc @@ -18,3 +18,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420/early_init.c b/src/mainboard/lenovo/t420/early_init.c new file mode 100644 index 0000000000..50e62586a5 --- /dev/null +++ b/src/mainboard/lenovo/t420/early_init.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +static void hybrid_graphics_init(void) +{ + bool peg, igd; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + if (peg && igd) + return; + + /* Hide disabled devices */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) + reg32 |= DEVEN_IGD; + else + /* Disable IGD VGA decode, no GTT or GFX stolen */ + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); +} + +void mainboard_pch_lpc_setup(void) +{ + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} + +// OC3 set in bios to port 2-7, OC7 set in bios to port 10-13 +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* P0: system port 4, OC0 */ + { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ + { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ + { 1, 0, -1 }, /* P3: WWAN, no OC */ + { 1, 0, -1 }, /* P4: smartcard, no OC */ + { 1, 1, -1 }, /* P5: ExpressCard, no OC */ + { 0, 0, -1 }, /* P6: empty */ + { 0, 0, -1 }, /* P7: empty */ + { 1, 1, 4 }, /* P8: system port 3, OC4*/ + { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 0, -1 }, /* P11: bluetooth, no OC. */ + { 1, 1, -1 }, /* P12: docking, no OC */ + { 1, 1, -1 }, /* P13: camera (LCD), no OC */ +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x51, id_only); +} + +void mainboard_early_init(int s3resume) +{ + hybrid_graphics_init(); +} diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c deleted file mode 100644 index e04803f165..0000000000 --- a/src/mainboard/lenovo/t420/romstage.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - -// OC3 set in bios to port 2-7, OC7 set in bios to port 10-13 -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, /* P0: system port 4, OC0 */ - { 1, 1, 1 }, /* P1: system port 2 (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 0, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 1, 1, 4 }, /* P8: system port 3, OC4*/ - { 1, 1, 5 }, /* P9: system port 1 (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 0, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} - -void mainboard_early_init(int s3resume) -{ - hybrid_graphics_init(); -} - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/lenovo/t420s/Makefile.inc b/src/mainboard/lenovo/t420s/Makefile.inc index 3914f51561..080812e44a 100644 --- a/src/mainboard/lenovo/t420s/Makefile.inc +++ b/src/mainboard/lenovo/t420s/Makefile.inc @@ -18,3 +18,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t420s/early_init.c b/src/mainboard/lenovo/t420s/early_init.c new file mode 100644 index 0000000000..1357a0ae52 --- /dev/null +++ b/src/mainboard/lenovo/t420s/early_init.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include + +static void hybrid_graphics_init(void) +{ + bool peg, igd; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + if (peg && igd) + return; + + /* Hide disabled devices */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) + reg32 |= DEVEN_IGD; + else + /* Disable IGD VGA decode, no GTT or GFX stolen */ + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); +} + +void mainboard_pch_lpc_setup(void) +{ + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 0, 1, -1 }, /* P0 empty */ + { 1, 1, 1 }, /* P1 system port 2 (To system port) (EHCI debug), OC 1 */ + { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ + { 1, 0, -1 }, /* P3: WWAN, no OC */ + { 1, 1, -1 }, /* P4: smartcard, no OC */ + { 1, 1, -1 }, /* P5: ExpressCard, no OC */ + { 0, 0, -1 }, /* P6: empty */ + { 0, 0, -1 }, /* P7: empty */ + { 0, 1, -1 }, /* P8: empty (touch panel) */ + { 1, 0, 5 }, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ + { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 1, -1 }, /* P11: bluetooth, no OC. */ + { 1, 1, -1 }, /* P12: docking, no OC */ + { 1, 1, -1 }, /* P13: camera (LCD), no OC */ +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x51, id_only); +} + +void mainboard_early_init(int s3resume) +{ + hybrid_graphics_init(); +} diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c deleted file mode 100644 index 764997297e..0000000000 --- a/src/mainboard/lenovo/t420s/romstage.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include - -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 0, 1, -1 }, /* P0 empty */ - { 1, 1, 1 }, /* P1 system port 2 (To system port) (EHCI debug), OC 1 */ - { 1, 1, -1 }, /* P2: HALF MINICARD (WLAN) no oc */ - { 1, 0, -1 }, /* P3: WWAN, no OC */ - { 1, 1, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 0, -1 }, /* P6: empty */ - { 0, 0, -1 }, /* P7: empty */ - { 0, 1, -1 }, /* P8: empty (touch panel) */ - { 1, 0, 5 }, /* P9: system port 1 (To USBAO) (EHCI debug), OC 5 */ - { 1, 0, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 1, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: camera (LCD), no OC */ -}; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} - -void mainboard_early_init(int s3resume) -{ - hybrid_graphics_init(); -} - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/lenovo/t430/Makefile.inc b/src/mainboard/lenovo/t430/Makefile.inc index 409d4842a9..0f49600c7d 100644 --- a/src/mainboard/lenovo/t430/Makefile.inc +++ b/src/mainboard/lenovo/t430/Makefile.inc @@ -1,6 +1,7 @@ -romstage-y += romstage.c bootblock-y += gpio.c romstage-y += gpio.c smm-y += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t430/early_init.c b/src/mainboard/lenovo/t430/early_init.c new file mode 100644 index 0000000000..74c8b60883 --- /dev/null +++ b/src/mainboard/lenovo/t430/early_init.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void hybrid_graphics_init(void) +{ + bool peg, igd; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + if (peg && igd) + return; + + /* Hide disabled devices */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) + reg32 |= DEVEN_IGD; + else + /* Disable IGD VGA decode, no GTT or GFX stolen */ + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); +} + +/* FIXME: used T530 values here */ +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 2, 3 }, + { 1, 1, -1 }, + { 1, 1, 2 }, + { 1, 0, -1 }, + { 0, 0, -1 }, + { 1, 2, -1 }, + { 1, 0, -1 }, + { 1, 1, 5 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 3, -1 }, + { 1, 1, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ + hybrid_graphics_init(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x51, id_only); +} diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c deleted file mode 100644 index f1e724be47..0000000000 --- a/src/mainboard/lenovo/t430/romstage.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Patrick Rudolph - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - -/* FIXME: used T530 values here */ -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, - { 1, 1, 1 }, - { 1, 2, 3 }, - { 1, 1, -1 }, - { 1, 1, 2 }, - { 1, 0, -1 }, - { 0, 0, -1 }, - { 1, 2, -1 }, - { 1, 0, -1 }, - { 1, 1, 5 }, - { 1, 0, -1 }, - { 1, 0, -1 }, - { 1, 3, -1 }, - { 1, 1, -1 }, -}; - -void mainboard_early_init(int s3resume) -{ - hybrid_graphics_init(); -} - -void mainboard_config_superio(void) -{ -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x51, id_only); -} diff --git a/src/mainboard/lenovo/t430s/Makefile.inc b/src/mainboard/lenovo/t430s/Makefile.inc index 425047fe44..d0e69a838f 100644 --- a/src/mainboard/lenovo/t430s/Makefile.inc +++ b/src/mainboard/lenovo/t430s/Makefile.inc @@ -20,3 +20,5 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads subdirs-$(CONFIG_BOARD_LENOVO_T431S) += variants/$(VARIANT_DIR)/spd +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t430s/early_init.c b/src/mainboard/lenovo/t430s/early_init.c new file mode 100644 index 0000000000..0757c06fbd --- /dev/null +++ b/src/mainboard/lenovo/t430s/early_init.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include + +void mainboard_pch_lpc_setup(void) +{ + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c deleted file mode 100644 index 6503c9a920..0000000000 --- a/src/mainboard/lenovo/t430s/romstage.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc index 5310bbf530..8f3c154418 100644 --- a/src/mainboard/lenovo/t520/Makefile.inc +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -18,3 +18,5 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t520/early_init.c b/src/mainboard/lenovo/t520/early_init.c new file mode 100644 index 0000000000..cfa69b7082 --- /dev/null +++ b/src/mainboard/lenovo/t520/early_init.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void hybrid_graphics_init(void) +{ + bool peg, igd; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + if (peg && igd) + return; + + /* Hide disabled devices */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) + reg32 |= DEVEN_IGD; + else + /* Disable IGD VGA decode, no GTT or GFX stolen */ + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); +} + +void mainboard_pch_lpc_setup(void) +{ + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, /* P0 left dual conn, OC 0 */ + { 1, 1, 1 }, /* P1 system onboard USB (eSATA), (EHCI debug), OC 1 */ + { 1, 2, -1 }, /* P2: wimax / WLAN */ + { 1, 1, -1 }, /* P3: WWAN, no OC */ + { 1, 1, -1 }, /* P4: smartcard, no OC */ + { 1, 1, -1 }, /* P5: ExpressCard, no OC */ + { 0, 2, -1 }, /* P6: empty */ + { 0, 2, -1 }, /* P7: to touch panel, no OC */ + { 1, 1, 4 }, /* P8: left dual conn, OC4 */ + { 1, 4, 5 }, /* P9: to system subcard back right, (EHCI debug), OC 5 */ + { 1, 1, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 2, -1 }, /* P11: bluetooth, no OC. */ + { 1, 1, -1 }, /* P12: docking, no OC */ + { 1, 1, -1 }, /* P13: CAMERA (LCD), no OC */ +}; + +void mainboard_early_init(int s3resume) +{ + hybrid_graphics_init(); +} diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c deleted file mode 100644 index caf54bd5df..0000000000 --- a/src/mainboard/lenovo/t520/romstage.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 1, 0 }, /* P0 left dual conn, OC 0 */ - { 1, 1, 1 }, /* P1 system onboard USB (eSATA), (EHCI debug), OC 1 */ - { 1, 2, -1 }, /* P2: wimax / WLAN */ - { 1, 1, -1 }, /* P3: WWAN, no OC */ - { 1, 1, -1 }, /* P4: smartcard, no OC */ - { 1, 1, -1 }, /* P5: ExpressCard, no OC */ - { 0, 2, -1 }, /* P6: empty */ - { 0, 2, -1 }, /* P7: to touch panel, no OC */ - { 1, 1, 4 }, /* P8: left dual conn, OC4 */ - { 1, 4, 5 }, /* P9: to system subcard back right, (EHCI debug), OC 5 */ - { 1, 1, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 2, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: docking, no OC */ - { 1, 1, -1 }, /* P13: CAMERA (LCD), no OC */ -}; - -void mainboard_early_init(int s3resume) -{ - hybrid_graphics_init(); -} - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc index 5310bbf530..8f3c154418 100644 --- a/src/mainboard/lenovo/t530/Makefile.inc +++ b/src/mainboard/lenovo/t530/Makefile.inc @@ -18,3 +18,5 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t530/early_init.c b/src/mainboard/lenovo/t530/early_init.c new file mode 100644 index 0000000000..34c61e4e49 --- /dev/null +++ b/src/mainboard/lenovo/t530/early_init.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void hybrid_graphics_init(void) +{ + bool peg, igd; + u32 reg32; + + early_hybrid_graphics(&igd, &peg); + + if (peg && igd) + return; + + /* Hide disabled devices */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); + + if (peg) + reg32 |= DEVEN_PEG10; + + if (igd) + reg32 |= DEVEN_IGD; + else + /* Disable IGD VGA decode, no GTT or GFX stolen */ + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); +} + +void mainboard_pch_lpc_setup(void) +{ + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} + +void mainboard_early_init(int s3resume) +{ + hybrid_graphics_init(); +} diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c deleted file mode 100644 index 85c3090bb5..0000000000 --- a/src/mainboard/lenovo/t530/romstage.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -static void hybrid_graphics_init(void) -{ - bool peg, igd; - u32 reg32; - - early_hybrid_graphics(&igd, &peg); - - if (peg && igd) - return; - - /* Hide disabled devices */ - reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); - reg32 &= ~(DEVEN_PEG10 | DEVEN_IGD); - - if (peg) - reg32 |= DEVEN_PEG10; - - if (igd) - reg32 |= DEVEN_IGD; - else - /* Disable IGD VGA decode, no GTT or GFX stolen */ - pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); - - pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); -} - -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - -void mainboard_early_init(int s3resume) -{ - hybrid_graphics_init(); -} - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/lenovo/x131e/Makefile.inc b/src/mainboard/lenovo/x131e/Makefile.inc index 4fbf73bbd3..1d258758be 100644 --- a/src/mainboard/lenovo/x131e/Makefile.inc +++ b/src/mainboard/lenovo/x131e/Makefile.inc @@ -17,3 +17,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x131e/early_init.c b/src/mainboard/lenovo/x131e/early_init.c new file mode 100644 index 0000000000..fe9fec0cb6 --- /dev/null +++ b/src/mainboard/lenovo/x131e/early_init.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2017 James Ye + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +const struct southbridge_usb_port mainboard_usb_ports[] = { + {1, 1, 0}, /* P0: USB 3.0 1 (OC0) */ + {1, 1, 0}, /* P1: USB 3.0 2 (OC0) */ + {0, 0, 0}, + {1, 1, -1}, /* P3: Camera (no OC) */ + {1, 0, -1}, /* P4: WLAN (no OC) */ + {1, 0, -1}, /* P5: WWAN (no OC) */ + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {1, 1, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ + {0, 0, 0}, + {0, 0, 0}, + {0, 0, 0}, + {1, 0, -1}, /* P13: Bluetooth (no OC) */ +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +} diff --git a/src/mainboard/lenovo/x131e/romstage.c b/src/mainboard/lenovo/x131e/romstage.c deleted file mode 100644 index 45d6b88099..0000000000 --- a/src/mainboard/lenovo/x131e/romstage.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2017 James Ye - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -const struct southbridge_usb_port mainboard_usb_ports[] = { - {1, 1, 0}, /* P0: USB 3.0 1 (OC0) */ - {1, 1, 0}, /* P1: USB 3.0 2 (OC0) */ - {0, 0, 0}, - {1, 1, -1}, /* P3: Camera (no OC) */ - {1, 0, -1}, /* P4: WLAN (no OC) */ - {1, 0, -1}, /* P5: WWAN (no OC) */ - {0, 0, 0}, - {0, 0, 0}, - {0, 0, 0}, - {1, 1, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ - {0, 0, 0}, - {0, 0, 0}, - {0, 0, 0}, - {1, 0, -1}, /* P13: Bluetooth (no OC) */ -}; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd(&spd[0], 0x50, id_only); - read_spd(&spd[2], 0x52, id_only); -} - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc index 8ce77fc77d..f6331a61d1 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc +++ b/src/mainboard/lenovo/x1_carbon_gen1/Makefile.inc @@ -20,3 +20,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c new file mode 100644 index 0000000000..c70b21d36b --- /dev/null +++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2017 Alexander Couzens + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void mainboard_pch_lpc_setup(void) +{ + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled, current, OC pin */ + { 0, 3, 0 }, /* P00 disconnected */ + { 1, 1, 1 }, /* P01 left or right */ + { 0, 1, 3 }, /* P02 disconnected */ + { 1, 3, -1 },/* P03 WWAN */ + { 0, 1, 2 }, /* P04 disconnected */ + { 0, 1, -1 },/* P05 disconnected */ + { 0, 1, -1 },/* P06 disconnected */ + { 0, 2, -1 },/* P07 disconnected */ + { 0, 1, -1 },/* P08 disconnected */ + { 1, 2, 5 }, /* P09 left or right */ + { 1, 3, -1 },/* P10 FPR */ + { 1, 3, -1 },/* P11 Bluetooth */ + { 1, 1, -1 },/* P12 WLAN */ + { 1, 1, -1 },/* P13 Camera */ +}; + +static uint8_t *get_spd_data(int spd_index) +{ + uint8_t *spd_file; + size_t spd_file_len; + + printk(BIOS_DEBUG, "spd index %d\n", spd_index); + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < spd_index * 256) + die("Missing SPD data."); + + return spd_file + spd_index * 256; +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + uint8_t *memory; + const int spd_gpio_vector[] = {25, 45, -1}; + int spd_index = get_gpios(spd_gpio_vector); + + /* 4gb model = 0, 8gb model = 1 */ + /* int extended_memory_version = get_gpio(44); */ + + /* + * So far there is no need to parse gpio 44, as the 4GiB use + * the hynix or elpida memory and 8 GiB versions use samsung. + * All version use both channels. + * But we might miss some versions. + */ + + /* + * GPIO45 GPIO25 + * 0 0 elpida + * 0 1 hynix + * 1 0 samsung + * 1 1 reserved + */ + + if (spd_index == 3) + die("Unsupported Memory. (detected 'reserved' memory configuration)."); + + memory = get_spd_data(spd_index); + memcpy(&spd[0], memory, 256); + memcpy(&spd[2], memory, 256); +} diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c deleted file mode 100644 index 1f027ffab8..0000000000 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * Copyright (C) 2017 Alexander Couzens - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - -const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled, current, OC pin */ - { 0, 3, 0 }, /* P00 disconnected */ - { 1, 1, 1 }, /* P01 left or right */ - { 0, 1, 3 }, /* P02 disconnected */ - { 1, 3, -1 },/* P03 WWAN */ - { 0, 1, 2 }, /* P04 disconnected */ - { 0, 1, -1 },/* P05 disconnected */ - { 0, 1, -1 },/* P06 disconnected */ - { 0, 2, -1 },/* P07 disconnected */ - { 0, 1, -1 },/* P08 disconnected */ - { 1, 2, 5 }, /* P09 left or right */ - { 1, 3, -1 },/* P10 FPR */ - { 1, 3, -1 },/* P11 Bluetooth */ - { 1, 1, -1 },/* P12 WLAN */ - { 1, 1, -1 },/* P13 Camera */ -}; - -static uint8_t *get_spd_data(int spd_index) -{ - uint8_t *spd_file; - size_t spd_file_len; - - printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < spd_index * 256) - die("Missing SPD data."); - - return spd_file + spd_index * 256; -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - uint8_t *memory; - const int spd_gpio_vector[] = {25, 45, -1}; - int spd_index = get_gpios(spd_gpio_vector); - - /* 4gb model = 0, 8gb model = 1 */ - /* int extended_memory_version = get_gpio(44); */ - - /* - * So far there is no need to parse gpio 44, as the 4GiB use - * the hynix or elpida memory and 8 GiB versions use samsung. - * All version use both channels. - * But we might miss some versions. - */ - - /* - * GPIO45 GPIO25 - * 0 0 elpida - * 0 1 hynix - * 1 0 samsung - * 1 1 reserved - */ - - if (spd_index == 3) - die("Unsupported Memory. (detected 'reserved' memory configuration)."); - - memory = get_spd_data(spd_index); - memcpy(&spd[0], memory, 256); - memcpy(&spd[2], memory, 256); -} - -void mainboard_config_superio(void) -{ -} diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc index c0ba457c57..4363770d28 100644 --- a/src/mainboard/lenovo/x220/Makefile.inc +++ b/src/mainboard/lenovo/x220/Makefile.inc @@ -19,3 +19,5 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c new file mode 100644 index 0000000000..8ee807cb5d --- /dev/null +++ b/src/mainboard/lenovo/x220/early_init.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void mainboard_pch_lpc_setup(void) +{ + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct pei_data pei_data_template = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = (uintptr_t)DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0x00,0xa2,0x00 }, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 1, + .gbe_enable = 1, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1333, + .usb_port_config = { + { 1, 0, 0x0040 }, + { 1, 1, 0x0080 }, + { 1, 3, 0x0080 }, + { 1, 3, 0x0080 }, + { 1, 0, 0x0080 }, + { 1, 0, 0x0080 }, + { 1, 2, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 6, 0x0080 }, + { 1, 5, 0x0080 }, + { 1, 6, 0x0080 }, + { 1, 6, 0x0080 }, + { 1, 7, 0x0080 }, + { 1, 6, 0x0080 }, + }, + }; + *pei_data = pei_data_template; +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd (&spd[0], 0x50, id_only); + read_spd (&spd[2], 0x51, id_only); +} + +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c deleted file mode 100644 index 72dd8dddca..0000000000 --- a/src/mainboard/lenovo/x220/romstage.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - struct pei_data pei_data_template = { - .pei_version = PEI_VERSION, - .mchbar = (uintptr_t)DEFAULT_MCHBAR, - .dmibar = (uintptr_t)DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = CONFIG_HPET_ADDRESS, - .rcba = (uintptr_t)DEFAULT_RCBABASE, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .thermalbase = 0xfed08000, - .system_type = 0, // 0 Mobile, 1 Desktop/Server - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa0, 0x00,0xa2,0x00 }, - .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, - .ec_present = 1, - .gbe_enable = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1333, - .usb_port_config = { - { 1, 0, 0x0040 }, - { 1, 1, 0x0080 }, - { 1, 3, 0x0080 }, - { 1, 3, 0x0080 }, - { 1, 0, 0x0080 }, - { 1, 0, 0x0080 }, - { 1, 2, 0x0040 }, - { 1, 2, 0x0040 }, - { 1, 6, 0x0080 }, - { 1, 5, 0x0080 }, - { 1, 6, 0x0080 }, - { 1, 6, 0x0080 }, - { 1, 7, 0x0080 }, - { 1, 6, 0x0080 }, - }, - }; - *pei_data = pei_data_template; -} - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd (&spd[0], 0x50, id_only); - read_spd (&spd[2], 0x51, id_only); -} - -void mainboard_config_superio(void) -{ -} - -int mainboard_should_reset_usb(int s3resume) -{ - return !s3resume; -} diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc index 3914f51561..080812e44a 100644 --- a/src/mainboard/lenovo/x230/Makefile.inc +++ b/src/mainboard/lenovo/x230/Makefile.inc @@ -18,3 +18,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x230/early_init.c b/src/mainboard/lenovo/x230/early_init.c new file mode 100644 index 0000000000..b737e7de83 --- /dev/null +++ b/src/mainboard/lenovo/x230/early_init.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +void mainboard_pch_lpc_setup(void) +{ + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, /* P0 (left, fan side), OC 0 */ + { 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */ + { 1, 1, 3 }, /* P2: dock, OC 3 */ + { 1, 1, -1 }, /* P3: wwan, no OC */ + { 1, 1, -1 }, /* P4: Wacom tablet on X230t, otherwise empty */ + { 1, 1, -1 }, /* P5: Expresscard, no OC */ + { 0, 0, -1 }, /* P6: Empty */ + { 1, 2, -1 }, /* P7: dock, no OC */ + { 1, 0, -1 }, + { 1, 2, 5 }, /* P9: Right (EHCI debug), OC 5 */ + { 1, 1, -1 }, /* P10: fingerprint reader, no OC */ + { 1, 1, -1 }, /* P11: bluetooth, no OC. */ + { 1, 1, -1 }, /* P12: wlan, no OC */ + { 1, 1, -1 }, /* P13: webcam, no OC */ +}; + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd (&spd[0], 0x50, id_only); + read_spd (&spd[2], 0x51, id_only); +} diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c deleted file mode 100644 index 56f5a90670..0000000000 --- a/src/mainboard/lenovo/x230/romstage.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -void mainboard_pch_lpc_setup(void) -{ - pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); -} - -const struct southbridge_usb_port mainboard_usb_ports[] = { - { 1, 0, 0 }, /* P0 (left, fan side), OC 0 */ - { 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */ - { 1, 1, 3 }, /* P2: dock, OC 3 */ - { 1, 1, -1 }, /* P3: wwan, no OC */ - { 1, 1, -1 }, /* P4: Wacom tablet on X230t, otherwise empty */ - { 1, 1, -1 }, /* P5: Expresscard, no OC */ - { 0, 0, -1 }, /* P6: Empty */ - { 1, 2, -1 }, /* P7: dock, no OC */ - { 1, 0, -1 }, - { 1, 2, 5 }, /* P9: Right (EHCI debug), OC 5 */ - { 1, 1, -1 }, /* P10: fingerprint reader, no OC */ - { 1, 1, -1 }, /* P11: bluetooth, no OC. */ - { 1, 1, -1 }, /* P12: wlan, no OC */ - { 1, 1, -1 }, /* P13: webcam, no OC */ -}; - -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd (&spd[0], 0x50, id_only); - read_spd (&spd[2], 0x51, id_only); -} - -void mainboard_config_superio(void) -{ -} -- cgit v1.2.3