From 99c45dee0ae62254be36a312d67764784450b564 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 15 Oct 2017 14:16:37 -0600 Subject: AMD GX2 boards & chips: Remove - using LATE_CBMEM_INIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/amd/geode_gx2 northbridge/amd/gx2 southbridge/amd/cs5535 Mainboards: mainboard/amd/rumba mainboard/lippert/frontrunner mainboard/wyse/s50 Change-Id: I81c130f53bbfa001edbfdb7a878ef115757f620c Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/22025 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/lippert/frontrunner/Kconfig | 27 ----- src/mainboard/lippert/frontrunner/Kconfig.name | 2 - src/mainboard/lippert/frontrunner/board_info.txt | 5 - src/mainboard/lippert/frontrunner/cmos.layout | 28 ----- src/mainboard/lippert/frontrunner/devicetree.cb | 20 ---- src/mainboard/lippert/frontrunner/irq_tables.c | 42 -------- src/mainboard/lippert/frontrunner/romstage.c | 127 ----------------------- 7 files changed, 251 deletions(-) delete mode 100644 src/mainboard/lippert/frontrunner/Kconfig delete mode 100644 src/mainboard/lippert/frontrunner/Kconfig.name delete mode 100644 src/mainboard/lippert/frontrunner/board_info.txt delete mode 100644 src/mainboard/lippert/frontrunner/cmos.layout delete mode 100644 src/mainboard/lippert/frontrunner/devicetree.cb delete mode 100644 src/mainboard/lippert/frontrunner/irq_tables.c delete mode 100644 src/mainboard/lippert/frontrunner/romstage.c (limited to 'src/mainboard/lippert') diff --git a/src/mainboard/lippert/frontrunner/Kconfig b/src/mainboard/lippert/frontrunner/Kconfig deleted file mode 100644 index 95dd96dfe8..0000000000 --- a/src/mainboard/lippert/frontrunner/Kconfig +++ /dev/null @@ -1,27 +0,0 @@ -if BOARD_LIPPERT_FRONTRUNNER - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_AMD_GEODE_GX2 - select NORTHBRIDGE_AMD_GX2 - select SOUTHBRIDGE_AMD_CS5535 - select SUPERIO_WINBOND_W83627HF - select HAVE_DEBUG_SMBUS - select UDELAY_TSC - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_256 - select GX2_PROCESSOR_MHZ_366 - -config MAINBOARD_DIR - string - default lippert/frontrunner - -config MAINBOARD_PART_NUMBER - string - default "Cool Frontrunner" - -config IRQ_SLOT_COUNT - int - default 2 - -endif # BOARD_LIPPERT_FRONTRUNNER diff --git a/src/mainboard/lippert/frontrunner/Kconfig.name b/src/mainboard/lippert/frontrunner/Kconfig.name deleted file mode 100644 index 4024a7b4d3..0000000000 --- a/src/mainboard/lippert/frontrunner/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_LIPPERT_FRONTRUNNER - bool "Cool FrontRunner" diff --git a/src/mainboard/lippert/frontrunner/board_info.txt b/src/mainboard/lippert/frontrunner/board_info.txt deleted file mode 100644 index a2b2d9f1e8..0000000000 --- a/src/mainboard/lippert/frontrunner/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Category: half -Board URL: http://www.lippertembedded.com/en/productoverview/products-in-detail/85-lipperts-cool-frontrunner.html -ROM package: PLCC -ROM protocol: FWH -ROM socketed: y diff --git a/src/mainboard/lippert/frontrunner/cmos.layout b/src/mainboard/lippert/frontrunner/cmos.layout deleted file mode 100644 index b8ea9363a4..0000000000 --- a/src/mainboard/lippert/frontrunner/cmos.layout +++ /dev/null @@ -1,28 +0,0 @@ -entries - -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -#392 3 r 0 unused -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -456 1 e 1 ECC_memory -1008 16 h 0 check_sum - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew - -checksums - -checksum 392 1007 1008 diff --git a/src/mainboard/lippert/frontrunner/devicetree.cb b/src/mainboard/lippert/frontrunner/devicetree.cb deleted file mode 100644 index 8e6cba0d76..0000000000 --- a/src/mainboard/lippert/frontrunner/devicetree.cb +++ /dev/null @@ -1,20 +0,0 @@ -chip northbridge/amd/gx2 - device cpu_cluster 0 on - chip cpu/amd/geode_gx2 - device lapic 0 on end - end - end - - device domain 0 on - device pci 0.0 on - chip southbridge/amd/cs5535 - register "setupflash" = "0" - device pci 12.0 on end - device pci 12.1 off end # SMI - device pci 12.2 on end # IDE - device pci 12.3 off end # Audio - device pci 12.4 off end # VGA - end - end - end -end diff --git a/src/mainboard/lippert/frontrunner/irq_tables.c b/src/mainboard/lippert/frontrunner/irq_tables.c deleted file mode 100644 index 25e2dcb99d..0000000000 --- a/src/mainboard/lippert/frontrunner/irq_tables.c +++ /dev/null @@ -1,42 +0,0 @@ -#include - -/* Platform IRQs */ -#define PIRQA 11 -#define PIRQB 5 -#define PIRQC 10 -#define PIRQD 10 - -/* Map */ -#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ -#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ -#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ -#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ - -/* Link */ -#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ -#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ -#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ -#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ - 0x00, /* Where the interrupt router lies (bus) */ - (0x12 << 3)|0x0, /* Where the interrupt router lies (dev) */ - 0x800, /* IRQs devoted exclusively to PCI usage */ - 0x1078, /* Vendor */ - 0x2, /* Device */ - 0, /* Miniport data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ - { - /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00,(0x0e << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, - {0x00,(0x0f << 3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, - } -}; -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c deleted file mode 100644 index e7fcbda8da..0000000000 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ /dev/null @@ -1,127 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "southbridge/amd/cs5535/early_smbus.c" -#include "southbridge/amd/cs5535/early_setup.c" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -static const unsigned char spdbytes[] = { /* 4x Qimonda HYB25DC512160CF-6 */ - 0xFF, 0xFF, /* only values used by raminit.c are set */ - [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, /* (Fundamental) memory type */ - [SPD_NUM_ROWS] = 0x0D, /* Number of row address bits [13] */ - [SPD_NUM_COLUMNS] = 0x0A, /* Number of column address bits [10] */ - [SPD_NUM_DIMM_BANKS] = 1, /* Number of module rows (banks) */ - 0xFF, 0xFF, 0xFF, - [SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 0x60, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) [6.0 ns in BCD] */ - 0xFF, 0xFF, - [SPD_REFRESH] = 0x82, /* Refresh rate/type [Self Refresh, 7.8 us] */ - [SPD_PRIMARY_SDRAM_WIDTH] = 64, /* SDRAM width (primary SDRAM) [64 bits] */ - 0xFF, 0xFF, 0xFF, - [SPD_NUM_BANKS_PER_SDRAM] = 4, /* SDRAM device attributes, number of banks on SDRAM device */ - [SPD_ACCEPTABLE_CAS_LATENCIES] = 0x1C, /* SDRAM device attributes, CAS latency [3, 2.5, 2] */ - 0xFF, 0xFF, - [SPD_MODULE_ATTRIBUTES] = 0x20, /* SDRAM module attributes [differential clk] */ - [SPD_DEVICE_ATTRIBUTES_GENERAL] = 0x40, /* SDRAM device attributes, general [Concurrent AP] */ - [SPD_SDRAM_CYCLE_TIME_2ND] = 0x60, /* SDRAM cycle time (2nd highest CAS latency) [6.0 ns in BCD] */ - 0xFF, - [SPD_SDRAM_CYCLE_TIME_3RD] = 0x75, /* SDRAM cycle time (3rd highest CAS latency) [7.5 ns in BCD] */ - 0xFF, - [SPD_tRP] = 72, /* Min. row precharge time [18 ns in units of 0.25 ns] */ - [SPD_tRRD] = 48, /* Min. row active to row active [12 ns in units of 0.25 ns] */ - [SPD_tRCD] = 72, /* Min. RAS to CAS delay [18 ns in units of 0.25 ns] */ - [SPD_tRAS] = 42, /* Min. RAS pulse width = active to precharge delay [42 ns] */ - [SPD_BANK_DENSITY] = 0x40, /* Density of each row on module [256 MB] */ - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - [SPD_tRFC] = 72 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh [72 ns] */ -}; - -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - if (device != DIMM0) - return 0xFF; /* No DIMM1, don't even try. */ - -#if IS_ENABLED(CONFIG_DEBUG_SMBUS) - if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) { - printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) " - "returns 0xff\n", address); - } -#endif - - /* Fake SPD ROM value */ - return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF; -} - -#include -#include "northbridge/amd/gx2/pll_reset.c" -#include "northbridge/amd/gx2/raminit.c" -#include "lib/generic_sdram.c" -#include "cpu/amd/geode_gx2/cpureginit.c" -#include "cpu/amd/geode_gx2/syspreinit.c" -#include "cpu/amd/geode_lx/msrinit.c" - -void asmlinkage mainboard_romstage_entry(unsigned long bist) -{ - static const struct mem_controller memctrl [] = { - {.channel0 = {DIMM0, DIMM1}} - }; - unsigned char temp; - - SystemPreInit(); - msr_init(); - - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - cs5535_early_setup(); - printk(BIOS_ERR, "done cs5535 early\n"); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - pll_reset(); - printk(BIOS_ERR, "done pll_reset\n"); - - cpuRegInit(); - printk(BIOS_ERR, "done cpuRegInit\n"); - - sdram_initialize(1, memctrl); - - printk(BIOS_ERR, "Done sdram_initialize\n"); - printk(BIOS_ERR, "Disable watchdog\n"); - outb( 0x87, 0x4E); //enter SuperIO configuration mode - outb( 0x87, 0x4E); - - outb(0x20, 0x4e); - temp = inb(0x4f); - printk(BIOS_DEBUG, "%02x", temp); - if (temp != 0x52){ - printk(BIOS_ERR, "CAN NOT READ SUPERIO VID\n"); - } - - outb(0x29, 0x4e); - outb(0x7c, 0x4f); - - outb( 0x07, 0x4E); //enable logical device 9 - outb( 0x09, 0x4F); - outb(0x30, 0x4e); - outb(1, 0x4f); - outb( 0xF0, 0x4E); //set GP33 as outbut in configuration register F0h Bit4 = \u20180\u2019 - outb( 0xC7, 0x4F); - outb( 0xF1, 0x4E); //clr GP33 (Bit4) value in cofiguration register F1h to \u20181\u2019 disables - temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged! - printk(BIOS_DEBUG, "%02x:", temp); - temp = temp & ~8; - outb( temp, 0x4F); - temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged! - printk(BIOS_DEBUG, "%02x\n", temp); -} -- cgit v1.2.3