From 9fee35c6c4aafd0f8c429263e24a7378dc138f02 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 23 Sep 2017 19:10:04 +0300 Subject: AGESA: Split long lines in OemCustomize.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I907f55622e6aaba401471239f706ab24cd26319f Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/21651 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- .../lippert/frontrunner-af/OemCustomize.c | 30 ++++++++++++++++++---- src/mainboard/lippert/toucan-af/OemCustomize.c | 30 ++++++++++++++++++---- 2 files changed, 50 insertions(+), 10 deletions(-) (limited to 'src/mainboard/lippert') diff --git a/src/mainboard/lippert/frontrunner-af/OemCustomize.c b/src/mainboard/lippert/frontrunner-af/OemCustomize.c index 02ef6de0db..7c6dc3380d 100644 --- a/src/mainboard/lippert/frontrunner-af/OemCustomize.c +++ b/src/mainboard/lippert/frontrunner-af/OemCustomize.c @@ -23,31 +23,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 0) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) + PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 0) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) + PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 0) }, // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) + PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 0) }, // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 0) } }; diff --git a/src/mainboard/lippert/toucan-af/OemCustomize.c b/src/mainboard/lippert/toucan-af/OemCustomize.c index 0bab96ff23..ea4c5af278 100644 --- a/src/mainboard/lippert/toucan-af/OemCustomize.c +++ b/src/mainboard/lippert/toucan-af/OemCustomize.c @@ -23,31 +23,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 0) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 0) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 0) }, // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 0) }, // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 0) } }; 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