From 6f2d20ec490a276a087acad0b3866c0f3ee844c4 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Wed, 6 Oct 2010 19:32:39 +0000 Subject: Convert all Intel 440BX boards to Cache-as-RAM (CAR). - Add "select CACHE_AS_RAM" in src/cpu/intel/slot_1/Kconfig. - Add the following in src/cpu/intel/slot_1/Makefile.inc: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc - Remove "select ROMCC" from all 440BX board Kconfig files. - Drop all early_mtrr_init() calls, that's done by CAR code now. Various small fixes were needed to make it build: - Drop do_smbus_recv_byte(), do_smbus_send_byte(), do_smbus_write_byte(), those were never called anyways. - Remove the "static" from the main() functions in romstage.c files. - Always call dump_spd_registers() from the 440BX debug.c, but use "#if CONFIG_DEBUG_RAM_SETUP" to only have that code if RAM debugging is enabled in menuconfig. - Drop all "lib/ramtest.c" #includes and ram_check() calls (even if commented out) from romstage.c's, as we've done for most other boards. - Add missing #includes or prototypes. Some of the prototypes will be removed later when we get rid of the #include'd .c files. Abuild-tested for all boards, and boot-tested on A-Trend ATC-6220. Signed-off-by: Uwe Hermann Acked-by: Patrick Georgi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5917 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/msi/ms6147/Kconfig | 1 - src/mainboard/msi/ms6147/romstage.c | 21 ++++----------------- 2 files changed, 4 insertions(+), 18 deletions(-) (limited to 'src/mainboard/msi/ms6147') diff --git a/src/mainboard/msi/ms6147/Kconfig b/src/mainboard/msi/ms6147/Kconfig index 198618f974..f126a6f08f 100644 --- a/src/mainboard/msi/ms6147/Kconfig +++ b/src/mainboard/msi/ms6147/Kconfig @@ -25,7 +25,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I440BX select SOUTHBRIDGE_INTEL_I82371EB select SUPERIO_WINBOND_W83977TF - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_256 diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index bcf5725f9b..2f84fbffd6 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -26,16 +26,15 @@ #include #include #include -#include "lib/ramtest.c" #include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" #include "northbridge/intel/i440bx/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include #include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -45,13 +44,10 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) } #include "northbridge/intel/i440bx/raminit.c" -/* #include "northbridge/intel/i440bx/debug.c" */ +#include "northbridge/intel/i440bx/debug.c" -static void main(unsigned long bist) +void main(unsigned long bist) { - if (bist == 0) - early_mtrr_init(); - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -61,17 +57,8 @@ static void main(unsigned long bist) i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */ enable_smbus(); - /* dump_spd_registers(); */ + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); -#if 0 - ram_check(0, 640 * 1024); /* DOS-area */ - ram_check(0x00100000, 0x00400000); /* 1MB to 4MB */ - ram_check(0x00100000, 0x03ffffff); /* 1MB to 64MB- */ - ram_check(0x03fff000, 0x04000010); /* Across 64MB boundary */ - ram_check(0x07ffff00, 0x07fffff0); /* Just below 128MB */ - ram_check(0x00100000, 0x07ffffff); /* 1MB to 128MB- */ -#endif } - -- cgit v1.2.3