From 0df0e14fb5b613e76ff022359c55d5df5633b40f Mon Sep 17 00:00:00 2001 From: "Jonathan A. Kollasch" Date: Mon, 1 Aug 2011 14:24:02 -0500 Subject: Add voltage control of southbridge and RAM on ms7135 Change-Id: I5d79b4838f69cad56d58363608b801f8b1d3ab43 Signed-off-by: Jonathan A. Kollasch Reviewed-on: http://review.coreboot.org/126 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/msi/ms7135/romstage.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'src/mainboard/msi/ms7135/romstage.c') diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 80b3c19bde..773d93e8dc 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -48,6 +48,10 @@ #include "cpu/amd/dualcore/dualcore.c" #include +#if CONFIG_HAVE_OPTION_TABLE +#include "option_table.h" +#endif + #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -66,6 +70,27 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" +static void ms7135_set_ram_voltage(void) +{ + u8 b; + b = read_option(ram_voltage, 0); + if (b > 4) /* default if above 2.70v */ + b = 0; + printk(BIOS_INFO, "setting RAM voltage %08x\n", b); + ck804_smbus_write_byte(1, 0x2f, 0x00, b); +} + +static void ms7135_set_nf4_voltage(void) +{ + u8 b; + b = read_option(nf4_voltage, 0); + if (b > 2) /* default if above 1.60v */ + b = 0; + b |= 0x10; + printk(BIOS_INFO, "setting NF4 voltage %08x\n", b); + ck804_smbus_write_byte(1, 0x2f, 0x02, b); +} + static void sio_setup(void) { u32 dword; @@ -136,6 +161,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_smbus(); + ms7135_set_nf4_voltage(); + ms7135_set_ram_voltage(); + #if CONFIG_DEBUG_SMBUS dump_spd_registers(&ctrl[0]); dump_smbus_registers(); -- cgit v1.2.3