From 57b2ff886e0ce2c92820f5722c8031def3ac94cf Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Sun, 21 Nov 2010 17:29:59 +0000 Subject: Drop excessive whitespace randomly sprinkled in romstage.c files. Also drop some dead or useless code snippets. Abuild-tested. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/msi/ms9282/romstage.c | 19 ++++--------------- 1 file changed, 4 insertions(+), 15 deletions(-) (limited to 'src/mainboard/msi/ms9282/romstage.c') diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index e7754d0535..dc9d946aed 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -31,29 +31,24 @@ #include #include #include - #include #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" - #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include - #include "northbridge/amd/amdk8/setup_resource_map.c" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) - #include #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" +#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) + static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -87,12 +82,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" - - /* msi does not want the default */ -#include "resourcemap.c" +#include "resourcemap.c" /* msi does not want the default */ #include "cpu/amd/dualcore/dualcore.c" - #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" + //set GPIO to input mode #define MCP55_MB_SETUP \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \ @@ -101,13 +94,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" - #include "cpu/amd/car/post_cache_as_ram.c" - #include "cpu/amd/model_fxx/init_cpus.c" // Disabled until it's actually used: // #include "cpu/amd/model_fxx/fidvid.c" - #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -210,4 +200,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } - -- cgit v1.2.3