From bcb8c97af94c9fc814fdbdafe5361666bf81d442 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Sun, 25 Apr 2010 18:06:32 +0000 Subject: try to unify timing initialization across those boards that need it... Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5496 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/msi/ms9282/romstage.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'src/mainboard/msi/ms9282/romstage.c') diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 87517f078c..ee44ea2ad3 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -199,16 +199,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn - needs_reset = optimize_link_coherent_ht(); + init_timer(); /* Need to use TMICT to synconize FID/VID. */ - needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= mcp55_early_setup_x(); - needs_reset |= mcp55_early_setup_x(); - - if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); - } + if (needs_reset) { + print_info("ht reset -\n"); + soft_reset(); + } //It's the time to set ctrl now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); @@ -226,6 +226,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); - } -- cgit v1.2.3