From 7b997053eb2fcde464f5f6a1e5c85d1ffb6b4e32 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Sun, 21 Nov 2010 22:47:22 +0000 Subject: Simplify a few code chunks, fix whitespace and indentation. Also, remove some less useful comments, some dead code / unused functions. Signed-off-by: Uwe Hermann Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/msi/ms7135/romstage.c | 21 ++++--------------- src/mainboard/msi/ms7260/romstage.c | 6 ------ src/mainboard/msi/ms9185/romstage.c | 34 ++++++++----------------------- src/mainboard/msi/ms9282/romstage.c | 15 ++++---------- src/mainboard/msi/ms9652_fam10/romstage.c | 17 +++------------- 5 files changed, 20 insertions(+), 73 deletions(-) (limited to 'src/mainboard/msi') diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 74e966d148..c804b6c9fe 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -50,15 +50,8 @@ #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) -{ - /* FIXME: Nothing to do? */ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* FIXME: Nothing to do? */ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { } static inline int spd_read_byte(unsigned device, unsigned address) { @@ -100,22 +93,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) }; int needs_reset; - unsigned bsp_apicid = 0; - + unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; - unsigned nodes; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - sio_setup(); } - if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - } w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -138,9 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif needs_reset |= ht_setup_chains_x(); - needs_reset |= ck804_early_setup_x(); - if (needs_reset) { print_info("ht reset -\n"); soft_reset(); diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 329c679dee..a3ea7d7f9f 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -117,7 +117,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset = 0; unsigned bsp_apicid = 0; @@ -125,10 +124,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Nothing special needs to be done to find bus 0. */ /* Allow the HT devices to be found. */ enumerate_ht_chain(); - sio_setup(); - - /* Setup the MCP55. */ mcp55_enable_rom(); } @@ -186,11 +182,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug_hex32(msr.lo); print_debug("\n"); } - enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); - { msr_t msr = rdmsr(0xc0010042); print_debug("end msr fid, vid "); diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 5c52dd29dd..ffe728d3e5 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -52,9 +52,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC) -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -85,7 +83,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" /* msi does not want the default */ +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include #include "cpu/amd/car/post_cache_as_ram.c" @@ -116,24 +114,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - bcm5785_enable_rom(); - bcm5785_enable_lpc(); - //enable RTC pc87417_enable_dev(RTC_DEV); } - if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - } - -// post_code(0x32); - pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -142,11 +133,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Halt if there was a built in self test failure */ report_bist_failure(bist); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_ms9185_resource_map(); #if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif @@ -166,7 +157,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif /* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn bcm5785_early_setup(); @@ -177,26 +168,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #endif #if CONFIG_SET_FIDVID - { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } - - enable_fid_change(); - - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); - // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } #endif diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index dc9d946aed..5036f17707 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -49,9 +49,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -59,7 +57,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) #define SMBUS_SWITCH2 0x72 unsigned device=(ctrl->channel0[0])>>8; smbus_send_byte(SMBUS_SWITCH1, device); - smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); + smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); } #if 0 @@ -68,7 +66,7 @@ static inline void change_i2c_mux(unsigned device) #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITHC2 0x72 smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); - smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); + smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); } #endif @@ -82,7 +80,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" /* msi does not want the default */ +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" @@ -138,12 +136,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - sio_setup(); - - /* Setup the mcp55 */ mcp55_enable_rom(); } @@ -177,7 +171,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); - if (needs_reset) { print_info("ht reset -\n"); soft_reset(); diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 8b297e0856..49b3e177c3 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -51,10 +51,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { } static inline int spd_read_byte(unsigned device, unsigned address) { @@ -110,31 +107,23 @@ static const u8 spd_addr[] = { void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - - u32 bsp_apicid = 0; - u32 val; + u32 bsp_apicid = 0, val, wants_reset; u8 reg; - u32 wants_reset; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - sio_setup(); - - /* Setup the mcp55 */ mcp55_enable_rom(); } post_code(0x30); - if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - } post_code(0x32); -- cgit v1.2.3