From cd49cce7b70e80b4acc49b56bb2bb94370b4d867 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 5 Mar 2019 16:53:33 -0800 Subject: coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX) This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/msi/ms7721/BiosCallOuts.c | 2 +- src/mainboard/msi/ms7721/OemCustomize.c | 4 ++-- src/mainboard/msi/ms7721/buildOpts.c | 2 +- src/mainboard/msi/ms7721/romstage.c | 4 ++-- src/mainboard/msi/ms9652_fam10/get_bus_conf.c | 2 +- src/mainboard/msi/ms9652_fam10/romstage.c | 4 ++-- 6 files changed, 9 insertions(+), 9 deletions(-) (limited to 'src/mainboard/msi') diff --git a/src/mainboard/msi/ms7721/BiosCallOuts.c b/src/mainboard/msi/ms7721/BiosCallOuts.c index c502d6a601..b3cac1d21e 100644 --- a/src/mainboard/msi/ms7721/BiosCallOuts.c +++ b/src/mainboard/msi/ms7721/BiosCallOuts.c @@ -65,7 +65,7 @@ static const CODEC_TBL_LIST CodecTableList[] = void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) { - FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); } void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) diff --git a/src/mainboard/msi/ms7721/OemCustomize.c b/src/mainboard/msi/ms7721/OemCustomize.c index 98b3478dc4..4782e11271 100644 --- a/src/mainboard/msi/ms7721/OemCustomize.c +++ b/src/mainboard/msi/ms7721/OemCustomize.c @@ -150,8 +150,8 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; - FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); - FchReset->Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = CONFIG(HUDSON_XHCI_ENABLE); } void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index f160745fcd..9e57e39613 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -167,7 +167,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if IS_ENABLED(CONFIG_GFXUMA) +#if CONFIG(GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 29880f48fd..0266eff5c4 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -117,9 +117,9 @@ void board_BeforeAgesa(struct sysinfo *cb) u8 byte; pci_devfn_t dev; - if (IS_ENABLED(CONFIG_POST_DEVICE_PCI_PCIE)) + if (CONFIG(POST_DEVICE_PCI_PCIE)) hudson_pci_port80(); - else if (IS_ENABLED(CONFIG_POST_DEVICE_LPC)) + else if (CONFIG(POST_DEVICE_LPC)) hudson_lpc_port80(); /* enable SIO LPC decode */ diff --git a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c index 8c7f921041..74b14b42c8 100644 --- a/src/mainboard/msi/ms9652_fam10/get_bus_conf.c +++ b/src/mainboard/msi/ms9652_fam10/get_bus_conf.c @@ -69,7 +69,7 @@ void get_bus_conf(void) } /*I/O APICs: APIC ID Version State Address*/ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + if (CONFIG(LOGICAL_CPUS)) { apicid_base = get_apicid_base(1); printk(BIOS_SPEW, "CONFIG_LOGICAL_CPUS == 1: apicid_base: %08x\n", apicid_base); } else { diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index ab9b0a4594..11015f6a67 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -186,7 +186,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); -- cgit v1.2.3