From 81725b2effe9269e5079c6043077ba516e72aa82 Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Wed, 20 Apr 2011 08:58:38 +0000 Subject: pci1x2x: remove latency/bridge control/cacheline size settings Those settings should be handled by the generic PCI/Cardbus code, and not by the driver itself. Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/nokia/ip530/devicetree.cb | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mainboard/nokia/ip530') diff --git a/src/mainboard/nokia/ip530/devicetree.cb b/src/mainboard/nokia/ip530/devicetree.cb index a132604472..f89d1cd9fe 100644 --- a/src/mainboard/nokia/ip530/devicetree.cb +++ b/src/mainboard/nokia/ip530/devicetree.cb @@ -33,8 +33,6 @@ chip northbridge/intel/i440bx # Northbridge device pci 00.0 on subsystemid 0x13b8 0x0000 end - register "cltr" = "0x40" - register "bcr" = "0x7c0" register "scr" = "0x08449060" register "mrr" = "0x00007522" end -- cgit v1.2.3