From 43927bae1846e0768cbfad717f4820f408cde82b Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 24 Jun 2017 21:54:33 -0600 Subject: mainboard/[m-w]: add IS_ENABLED() around Kconfig symbol references Change-Id: Ifba3257b0328d0b6ad1bee9bf885683998df5851 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/20344 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/nvidia/l1_2pvv/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/nvidia') diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index b80f4f37d4..9c04b1cadc 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -142,7 +142,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) { msr_t msr; msr = rdmsr(0xc0010042); -- cgit v1.2.3