From 9068788a8f0c96a5153fcd4e5ed80eac80b060c6 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Mon, 26 May 2014 04:03:24 +1000 Subject: superio/winbond/w83627ehg: Depreciate romstage component MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Part 1/2: These are actually not necessary if Super I/O support is properly utilized. Change-Id: I39b621e582f8d0762276d29492c91dce500f0665 Signed-off-by: Edward O'Callaghan Reviewed-on: http://review.coreboot.org/5870 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/nvidia/l1_2pvv/romstage.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mainboard/nvidia') diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index d411354428..df78a0c622 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -36,6 +36,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" +#include #include #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -119,11 +120,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x24, 0); - w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); setup_mb_resource_map(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ -- cgit v1.2.3