From e4aab352ee2d3981f5ec8d28a77ee93163fdf365 Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Fri, 26 Jun 2020 14:36:01 -0700 Subject: vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt soc CPX-SP FSP ww26 release added UPDs to allow FSP serial redirection. Also update memory map HOB definition file accordingly. The CPX-SP soc code is updated to direct FSP log to SOL. Signed-off-by: Jonathan Zhang Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf Reviewed-on: https://review.coreboot.org/c/coreboot/+/42840 Reviewed-by: Christian Walter Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/ocp/deltalake/romstage.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/mainboard/ocp/deltalake') diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 35c7e2d14b..fb9a549033 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -14,7 +14,9 @@ static void mainboard_config_gpios(FSPM_UPD *mupd) static void mainboard_config_iio(FSPM_UPD *mupd) { - /* To be implemented */ + /* Send FSP log message to SOL */ + mupd->FspmConfig.SerialIoUartDebugEnable = 1; + mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8; } void mainboard_memory_init_params(FSPM_UPD *mupd) -- cgit v1.2.3