From 2c3fd499cf0672a8da669e40be84112a02b5a77c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 22 Jul 2016 22:52:14 +0300 Subject: intel/nehalem post-car: Use postcar_frame for MTRR setup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Change-Id: I84f6fa6f37a7348b2d4ad9f08a18bebe4b1e34e2 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15793 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/packardbell/ms2290/romstage.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'src/mainboard/packardbell/ms2290') diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 31b8f76b01..a52f153e59 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -269,11 +269,8 @@ void mainboard_romstage_entry(unsigned long bist) outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); } - romstage_handoff_init(s3resume); - if (s3resume) - acpi_prepare_for_resume(); - else + if (!s3resume) quick_ram_check(); } -- cgit v1.2.3