From c04871a398ca945b42fde0867572094c38f6f92c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 20 Mar 2020 16:14:36 +0100 Subject: mb/pcengines/apu2: add reset logic for PCIe slots MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PC Engines apu2 had many problems with PCIe cards detection. The cards were inconsistently detected when booted from G3, S5 or after a reboot. AGESA can reset PCIe slots using GPIO via callback. Use it to reset the slots that support using GPIO as reset signal. Signed-off-by: Michał Żygowski Change-Id: I8ff7db6ff85cce45b84729be905e6c895a24f6f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39703 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/pcengines/apu2/OemCustomize.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) (limited to 'src/mainboard/pcengines/apu2/OemCustomize.c') diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 99b9d518e7..6339e0fc4a 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -15,6 +15,15 @@ #include #include +#define PCIE_NIC_RESET_ID 1 + +#if CONFIG(BOARD_PCENGINES_APU2) +#define PCIE_GFX_RESET_ID 55 +#define PCIE_PORT3_RESET_ID 51 +#else +#define PCIE_GFX_RESET_ID PCIE_NIC_RESET_ID +#define PCIE_PORT3_RESET_ID PCIE_NIC_RESET_ID +#endif static const PCIe_PORT_DESCRIPTOR PortList[] = { { @@ -24,7 +33,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x01, 0) + AspmDisabled, PCIE_PORT3_RESET_ID, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { @@ -34,7 +43,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x02, 0) + AspmDisabled, PCIE_NIC_RESET_ID, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { @@ -44,7 +53,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x03, 0) + AspmDisabled, PCIE_NIC_RESET_ID, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { @@ -54,7 +63,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x04, 0) + AspmDisabled, PCIE_NIC_RESET_ID, 0) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { @@ -64,7 +73,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, - AspmDisabled, 0x05, 0) + AspmDisabled, PCIE_GFX_RESET_ID, 0) } }; -- cgit v1.2.3