From 1749f272758b59f1717d34a5f1c67710f29cfbb5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 30 Apr 2021 12:43:41 +0200 Subject: mb/pcengines/apu1: Disable memory bank interleaving MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bank interleaving does not work on this platform, disable it. AmdInitPost returns success thanks to this setting. TEST=boot apu1 and see AGESA_SUCCESS after AmdInitPost Signed-off-by: Michał Żygowski Change-Id: Id555b458c61df9a27a93f44f600d1718867106ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/52779 Tested-by: build bot (Jenkins) Reviewed-by: Krystian Hebel Reviewed-by: Angel Pons --- src/mainboard/pcengines/apu1/OemCustomize.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/pcengines') diff --git a/src/mainboard/pcengines/apu1/OemCustomize.c b/src/mainboard/pcengines/apu1/OemCustomize.c index d6edf03e8b..254947cf8c 100644 --- a/src/mainboard/pcengines/apu1/OemCustomize.c +++ b/src/mainboard/pcengines/apu1/OemCustomize.c @@ -101,4 +101,6 @@ static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) { InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; + /* Bank interleaving is not supported on this platform */ + InitPost->MemConfig.EnableBankIntlv = FALSE; } -- cgit v1.2.3