From af258cc1791b5c46fcb13d41128cc99043a435be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Sun, 1 Dec 2019 17:42:04 +0100 Subject: mb/*/*: use ACPIMMIO common block wherever possible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TEST=boot PC Engines apu2 and launch Debian Linux Signed-off-by: Michał Żygowski Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37401 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/pcengines/apu1/gpio_ftns.c | 16 ++++----- src/mainboard/pcengines/apu1/gpio_ftns.h | 4 +-- src/mainboard/pcengines/apu1/mainboard.c | 19 ++++++----- src/mainboard/pcengines/apu2/gpio_ftns.c | 56 ++++++++++++++++++++++---------- src/mainboard/pcengines/apu2/gpio_ftns.h | 2 +- 5 files changed, 57 insertions(+), 40 deletions(-) (limited to 'src/mainboard/pcengines') diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.c b/src/mainboard/pcengines/apu1/gpio_ftns.c index 4e58d5593b..206dc63c9d 100644 --- a/src/mainboard/pcengines/apu1/gpio_ftns.c +++ b/src/mainboard/pcengines/apu1/gpio_ftns.c @@ -27,25 +27,21 @@ uintptr_t find_gpio_base(void) return base_addr; } -void configure_gpio(uintptr_t base_addr, u32 gpio, u8 iomux_ftn, u8 setting) +void configure_gpio(uintptr_t base_addr, u8 gpio, u8 iomux_ftn, u8 setting) { u8 bdata; - u8 *memptr; - memptr = (u8 *)(base_addr + IOMUX_OFFSET + gpio); - *memptr = iomux_ftn; + iomux_write8(gpio, iomux_ftn); - memptr = (u8 *)(base_addr + GPIO_OFFSET + gpio); - bdata = *memptr; + bdata = gpio_100_read8(gpio); bdata &= 0x07; bdata |= setting; /* set direction and data value */ - *memptr = bdata; + gpio_100_write8(gpio, bdata); } -u8 read_gpio(uintptr_t base_addr, u32 gpio) +u8 read_gpio(uintptr_t base_addr, u8 gpio) { - u8 *memptr = (u8 *)(base_addr + GPIO_OFFSET + gpio); - return (*memptr & GPIO_DATA_IN) ? 1 : 0; + return (gpio_100_read8(gpio) & GPIO_DATA_IN) ? 1 : 0; } int get_spd_offset(void) diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.h b/src/mainboard/pcengines/apu1/gpio_ftns.h index fce8afe6f0..fb582721d2 100644 --- a/src/mainboard/pcengines/apu1/gpio_ftns.h +++ b/src/mainboard/pcengines/apu1/gpio_ftns.h @@ -19,8 +19,8 @@ #include uintptr_t find_gpio_base(void); -void configure_gpio(uintptr_t base_addr, u32 gpio, u8 iomux_ftn, u8 setting); -u8 read_gpio(uintptr_t base_addr, u32 gpio); +void configure_gpio(uintptr_t base_addr, u8 gpio, u8 iomux_ftn, u8 setting); +u8 read_gpio(uintptr_t base_addr, u8 gpio); int get_spd_offset(void); #define IOMUX_OFFSET 0xD00 diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 854fb8ad4d..0528468e5d 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -181,17 +182,17 @@ static void mainboard_enable(struct device *dev) config_gpio_mux(); config_addon_uart(); - /* Power off unused clock pins of GPP PCIe devices */ - u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); - /* GPP CLK0-2 are connected to the 3 ethernet chips - * GPP CLK3-4 are connected to the miniPCIe slots */ - write8(misc_mem_clk_cntrl + 0, 0x21); - write8(misc_mem_clk_cntrl + 1, 0x43); + /* Power off unused clock pins of GPP PCIe devices + * GPP CLK0-2 are connected to the 3 ethernet chips + * GPP CLK3-4 are connected to the miniPCIe slots + */ + misc_write8(0, 0x21); + misc_write8(1, 0x43); /* GPP CLK5 is only connected to test pads -> disable */ - write8(misc_mem_clk_cntrl + 2, 0x05); + misc_write8(2, 0x05); /* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */ - write8(misc_mem_clk_cntrl + 3, 0x00); - write8(misc_mem_clk_cntrl + 4, 0x00); + misc_write8(3, 0); + misc_write8(4, 0); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.c b/src/mainboard/pcengines/apu2/gpio_ftns.c index 249ecc3494..170acca8d3 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.c +++ b/src/mainboard/pcengines/apu2/gpio_ftns.c @@ -14,55 +14,75 @@ */ #include +#include +#include #include #include #include "gpio_ftns.h" -void configure_gpio(u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting) +static u32 gpio_read_wrapper(u32 gpio) +{ + if (gpio < 0x100) + return gpio0_read32(gpio & 0xff); + else if (gpio >= 0x100 && gpio < 0x200) + return gpio1_read32(gpio & 0xff); + else if (gpio >= 0x200 && gpio < 0x300) + return gpio2_read32(gpio & 0xff); + + die("Invalid GPIO"); +} + +static void gpio_write_wrapper(u32 gpio, u32 setting) +{ + if (gpio < 0x100) + gpio0_write32(gpio & 0xff, setting); + else if (gpio >= 0x100 && gpio < 0x200) + gpio1_write32(gpio & 0xff, setting); + else if (gpio >= 0x200 && gpio < 0x300) + gpio2_write32(gpio & 0xff, setting); +} + +void configure_gpio(u8 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting) { u32 bdata; - bdata = read32((const volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET - + gpio)); + bdata = gpio_read_wrapper(gpio); /* out the data value to prevent glitches */ bdata |= (setting & GPIO_OUTPUT_ENABLE); - write32((volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio), bdata); + gpio_write_wrapper(gpio, bdata); /* set direction and data value */ bdata |= (setting & (GPIO_OUTPUT_ENABLE | GPIO_OUTPUT_VALUE | GPIO_PULL_UP_ENABLE | GPIO_PULL_DOWN_ENABLE)); - write32((volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio), bdata); + gpio_write_wrapper(gpio, bdata); - write8((volatile void *)(ACPI_MMIO_BASE + IOMUX_OFFSET + iomux_gpio), - iomux_ftn & 0x3); + iomux_write8(iomux_gpio, iomux_ftn & 0x3); } u8 read_gpio(u32 gpio) { - u32 status = read32((const volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET - + gpio)); - - return (status & GPIO_PIN_STS) ? 1 : 0; + return (gpio_read_wrapper(gpio) & GPIO_PIN_STS) ? 1 : 0; } void write_gpio(u32 gpio, u8 value) { - u32 status = read32((const volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET - + gpio)); + u32 status = gpio_read_wrapper(gpio); status &= ~GPIO_OUTPUT_VALUE; status |= (value > 0) ? GPIO_OUTPUT_VALUE : 0; - write32((volatile void *)(ACPI_MMIO_BASE + GPIO_OFFSET + gpio), status); + gpio_write_wrapper(gpio, status); } int get_spd_offset(void) { u8 index = 0; - /* One SPD file contains all 4 options, determine which index to + /* + * One SPD file contains all 4 options, determine which index to * read here, then call into the standard routines. */ - u8 *gpio_bank0_ptr = (u8 *)(ACPI_MMIO_BASE + GPIO_BANK0_BASE); - if (*(gpio_bank0_ptr + (0x40 << 2) + 2) & BIT0) index |= BIT0; - if (*(gpio_bank0_ptr + (0x41 << 2) + 2) & BIT0) index |= BIT1; + if (gpio1_read8(0x02) & BIT0) + index |= BIT0; + if (gpio1_read8(0x06) & BIT0) + index |= BIT1; return index; } diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h index 24d6a7f772..49169be121 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.h +++ b/src/mainboard/pcengines/apu2/gpio_ftns.h @@ -16,7 +16,7 @@ #ifndef GPIO_FTNS_H #define GPIO_FTNS_H -void configure_gpio(u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting); +void configure_gpio(u8 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting); u8 read_gpio(u32 gpio); void write_gpio(u32 gpio, u8 value); int get_spd_offset(void); -- cgit v1.2.3