From fba03208428fd11acc69e0b3b00bf358cc83f7de Mon Sep 17 00:00:00 2001 From: Krystian Hebel Date: Fri, 21 Dec 2018 18:19:14 +0100 Subject: mb/pcengines/apu2/romstage.c: disable SVI2 wait completion MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On some platforms SVI command completion is not reported by voltage regulator. Because of that CPU got stuck in invalid P-State, which resulted in lower frequency and inability to reboot platform without performing cold reset. Change-Id: I260c997f3a0f4547041785a3b9de78e34d22812a Signed-off-by: Krystian Hebel Reviewed-on: https://review.coreboot.org/c/30367 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski Reviewed-by: Piotr Król Reviewed-by: Patrick Georgi --- src/mainboard/pcengines/apu2/romstage.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/mainboard/pcengines') diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index a4bd816506..a1720d2ab4 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -105,6 +105,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); + /* Disable SVI2 controller to wait for command completion */ + val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); + if (val & (1 << 30)) { + printk(BIOS_DEBUG, "SVI2 Wait completion disabled\n"); + } else { + printk(BIOS_DEBUG, "Disabling SVI2 Wait completion\n"); + val |= (1 << 30); + pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val); + } + timestamp_add_now(TS_BEFORE_INITRAM); post_code(0x40); -- cgit v1.2.3