From ed52e3dd9c33e5f714bde615e16c1b187cdd269f Mon Sep 17 00:00:00 2001
From: Frans Hendriks <fhendriks@eltan.com>
Date: Mon, 15 Jul 2019 08:48:55 +0200
Subject: mainboard/portwell/m107: Do initial mainboard commit

Initial support for Portwell PQ7-M107 (Q7) module.
Code based on Intel Strago mainboard.

BUG=N/A
TEST=booting SeaBIOS and Linux 4.20 kernel on PQ7-M107

Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
---
 src/mainboard/portwell/m107/dsdt.asl | 48 ++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 src/mainboard/portwell/m107/dsdt.asl

(limited to 'src/mainboard/portwell/m107/dsdt.asl')

diff --git a/src/mainboard/portwell/m107/dsdt.asl b/src/mainboard/portwell/m107/dsdt.asl
new file mode 100644
index 0000000000..4eea7b93f4
--- /dev/null
+++ b/src/mainboard/portwell/m107/dsdt.asl
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2015-2018 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		/* DSDT revision: ACPI v2.0 and up */
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	/* OEM revision */
+)
+{
+	/* Some generic macros */
+	#include <acpi/platform.asl>
+
+	/* global NVS and variables */
+	#include <acpi/globalnvs.asl>
+
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <acpi/southcluster.asl>
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include "acpi/sleepstates.asl"
+	#include "acpi/mainboard.asl"
+}
-- 
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