From 8d98d80e5330f465c315a7aade4b754b8c6c79b3 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Mon, 9 Dec 2019 10:02:26 +0100 Subject: mb/portwell/m107/devicetree.cb: Use IGD_MEMSIZE_32MB Make code more readable. Replace 1 by IGD_MEMSIZE_32MB for PcdIgdDvmtS0PreAlloc. BUG=N/A TEST=build Change-Id: I5d84e575935e9e60610e1805e1402f290672b114 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/37616 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/portwell/m107/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/portwell') diff --git a/src/mainboard/portwell/m107/devicetree.cb b/src/mainboard/portwell/m107/devicetree.cb index 9a27fed8cf..f68b071a12 100644 --- a/src/mainboard/portwell/m107/devicetree.cb +++ b/src/mainboard/portwell/m107/devicetree.cb @@ -9,7 +9,7 @@ chip soc/intel/braswell register "PcdMrcInitMmioSize" = "0x0800" register "PcdMrcInitSpdAddr1" = "0xa0" register "PcdMrcInitSpdAddr2" = "0xa2" - register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_32MB" register "PcdApertureSize" = "2" register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" -- cgit v1.2.3