From 6aa28d93b354845e96c7154b1670864fa48ac16a Mon Sep 17 00:00:00 2001 From: Youness Alaoui Date: Tue, 13 Mar 2018 16:53:30 -0400 Subject: purism/librem13v1, librem13v2, liberm15v3: Fix EC LPC I/O port The LPC I/O ports for EC communication were not set properly, causing ectool to fail to read the Index I/O from the EC. The EC Index I/O is on port 0x380 and the LPC I/O port needs to be decoded by the PCI device for it to be accessible. Correct the value for the Librem 13v1, 13v2 and 15v3. Change-Id: Ide1d158340eadfabbce5f70ceccddfabb4db188a Signed-off-by: Youness Alaoui Reviewed-on: https://review.coreboot.org/25328 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/mainboard/purism/librem13v1/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/purism/librem13v1') diff --git a/src/mainboard/purism/librem13v1/devicetree.cb b/src/mainboard/purism/librem13v1/devicetree.cb index ba38070a55..c916e9a9a4 100644 --- a/src/mainboard/purism/librem13v1/devicetree.cb +++ b/src/mainboard/purism/librem13v1/devicetree.cb @@ -18,6 +18,10 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f + register "gen1_dec" = "0x00000381" + register "gen2_dec" = "0x000c0081" + # Port 0 is HDD # Port 3 is M.2 NGFF register "sata_port_map" = "0x9" -- cgit v1.2.3