From 54e0fd21b1f916a3f152114027db1029a921fc55 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 29 Oct 2020 20:30:08 -0500 Subject: mb/purism/librem_whl: rename to librem_cnl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since Whiskeylake SoC code is actually a subset of soc/intel/cannonlake, rename the baseboard so that boards using other 'cannonlake family' SoCs (e.g., Cometlake) can be added with minimal confusion. Rename the mainboard dir and baseboard name, and adjust any references to them. Change-Id: I2af7977f1622070eb8bf8449bc8306f9d75b9851 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47050 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/mainboard/purism/librem_cnl/romstage.c | 59 ++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 src/mainboard/purism/librem_cnl/romstage.c (limited to 'src/mainboard/purism/librem_cnl/romstage.c') diff --git a/src/mainboard/purism/librem_cnl/romstage.c b/src/mainboard/purism/librem_cnl/romstage.c new file mode 100644 index 0000000000..3a3ca6b491 --- /dev/null +++ b/src/mainboard/purism/librem_cnl/romstage.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct cnl_mb_cfg memcfg = { + + /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0}, + }, + .spd[1] = {.read_type = NOT_EXISTING}, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + .spd[3] = {.read_type = NOT_EXISTING}, + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + .rcomp_resistor = { 121, 81, 100 }, + + /* Rcomp target values */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* + * Indicates whether memory is interleaved. + * Set to 1 for an interleaved design, + * set to 0 for non-interleaved design. + */ + .dq_pins_interleaved = 1, + + /* + * VREF_CA configuration. + * Set to 0 VREF_CA goes to both CH_A and CH_B, + * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, + * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + */ + .vref_ca_config = 2, + + /* Early Command Training */ + .ect = 0, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + cannonlake_memcfg_init(mem_cfg, &memcfg); + + /* Enable and set SATA HSIO adjustments for ports 0 and 2 */ + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[0] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMagEnable[2] = 1; + mem_cfg->PchSataHsioRxGen3EqBoostMag[0] = 2; + mem_cfg->PchSataHsioRxGen3EqBoostMag[2] = 1; +} -- cgit v1.2.3