From 0d29bb72a18a5e4866c4494bf509f1e7dd954003 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 3 Nov 2020 13:27:43 -0600 Subject: mb/purism_librem_mini: Add child device, slot descriptions to PCIe RPs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Id306100fc691dcbde48b65092d0be9d7e73c0722 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47189 Reviewed-by: Stefan Reinauer Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- .../purism/librem_cnl/variants/librem_mini/devicetree.cb | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) (limited to 'src/mainboard/purism/librem_cnl') diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index c69f3f635e..9fde5e97da 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -204,22 +204,29 @@ chip soc/intel/cannonlake device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on # PCI Express Port 8 (WLAN) + device pci 1c.7 on # PCI Express Port 8 + chip drivers/wifi/generic + device pci 00.0 on end # x1 M.2/E 2230 (WLAN) + end register "PcieRpSlotImplemented[7]" = "1" register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" end device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 on # PCI Express Port 10 (LAN) + device pci 1d.1 on # PCI Express Port 10 + device pci 00.0 on end # x1 (LAN) register "PcieRpSlotImplemented[9]" = "1" register "PcieRpEnable[9]" = "1" end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on # PCI Express Port 13 (NVMe) + device pci 1d.4 on # PCI Express Port 13 + device pci 00.0 on end # x4 M.2/M 2280 (NVMe) register "PcieRpSlotImplemented[12]" = "1" register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 -- cgit v1.2.3