From f5116952bb77ac361ad541dea00d9df28067219e Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 26 Mar 2018 02:24:18 -0700 Subject: soc/intel/skylake: Limit xDCI feature when VBOOT is enabled Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb and the mainboards that had defined it were adjusted accordingly. This was tested on an Eve board with xDCI enabled in devicetree.cb to ensure the xDCI device is enabled in developer mode and disabled in normal mode. Change-Id: Ic3c84beac87452f17490de32082030880834501d Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/25365 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb | 1 - src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb | 1 - 2 files changed, 2 deletions(-) (limited to 'src/mainboard/purism/librem_skl') diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb index 50e484b0df..b3c5ffb51d 100644 --- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb @@ -41,7 +41,6 @@ chip soc/intel/skylake register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb index a52e4b7e3f..bf57398e9a 100644 --- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb +++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb @@ -41,7 +41,6 @@ chip soc/intel/skylake register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "EnableTraceHub" = "0" - register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" register "Cio2Enable" = "0" -- cgit v1.2.3