From c5f1dc96bf0b18245d7986463ae56958c44d24f2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sat, 10 Apr 2021 22:51:15 +0200 Subject: mb/*: drop LPC generic range for port 80 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have to be set up as generic range. Drop the entries from the devicetrees. Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/razer/blade_stealth_kbl/devicetree.cb | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/mainboard/razer') diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index a358fb8374..a4951fe9de 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -15,9 +15,8 @@ chip soc/intel/skylake register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" - register "gen1_dec" = "0x000c0081" - register "gen2_dec" = "0x000c0681" - register "gen3_dec" = "0x000c1641" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" # Disable DPTF register "dptf_enable" = "0" -- cgit v1.2.3