From 07921540dda79d810d8bfc6be211513c238a0d63 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 17 Jun 2016 17:22:00 +0300 Subject: intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I02881ce465cb3835a6fa7c06b718aa42d0d327ec Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15227 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/mainboard/rca/rm4100/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/rca/rm4100') diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index 296d072e23..43c518f428 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -27,6 +27,7 @@ #include #include "southbridge/intel/i82801dx/reset.c" #include +#include #include "spd_table.h" #include "gpio.c" #include "southbridge/intel/i82801dx/tco_timer.c" @@ -88,8 +89,7 @@ static void mb_early_setup(void) pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10); } -#include -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { if (bist == 0) { if (memory_initialized()) -- cgit v1.2.3