From e8e66f47631c505ab153d8a348058350b9acfe88 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sat, 6 Feb 2016 17:42:42 +0100 Subject: southbridge/intel/bd82x6x: Use common gpio.c Use shared gpio code from common folder. Bd82x6x's gpio.c and gpio.h is used by other southbridges as well and will be removed once it is unused. Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/13614 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/samsung/lumpy/chromeos.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'src/mainboard/samsung/lumpy/chromeos.c') diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c index 4bf69689b3..9ee32bb7c6 100644 --- a/src/mainboard/samsung/lumpy/chromeos.c +++ b/src/mainboard/samsung/lumpy/chromeos.c @@ -20,6 +20,7 @@ #include #include #include +#include #define GPIO_SPI_WP 24 #define GPIO_REC_MODE 42 @@ -119,19 +120,16 @@ int get_recovery_mode_switch(void) void init_bootmode_straps(void) { #ifdef __PRE_RAM__ - u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe; - u32 gp_lvl2 = inl(gpio_base + GP_LVL2); - u32 gp_lvl = inl(gpio_base + GP_LVL); u32 flags = 0; /* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */ - if (gp_lvl & (1 << GPIO_SPI_WP)) + if (get_gpio(GPIO_SPI_WP)) flags |= (1 << FLAG_SPI_WP); /* Recovery: GPIO42 = CHP3_REC_MODE#, active low */ - if (!(gp_lvl2 & (1 << (GPIO_REC_MODE-32)))) + if (!get_gpio(GPIO_REC_MODE)) flags |= (1 << FLAG_REC_MODE); /* Developer: GPIO17 = KBC3_DVP_MODE, active high */ - if (gp_lvl & (1 << GPIO_DEV_MODE)) + if (get_gpio(GPIO_DEV_MODE)) flags |= (1 << FLAG_DEV_MODE); pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); -- cgit v1.2.3