From b30a47b841f1c7d55d9cf207e1cc89f1b7f7fa51 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 15 Jul 2019 18:04:23 +0200 Subject: sb/intel/{bd82x6x|ibexpeak}: Drop p_cnt_throttling_supported The processor P_BLK doesn't support throttling. This behaviour could be emulated with SMM, but instead just update the FADT to indicate no support for legacy I/O based throttling using P_CNT. We have _PTC defined in SSDT, which should be used in favour of P_CNT by ACPI aware OS, so this change has no effect on modern OS. Drop all occurences of p_cnt_throttling_supported and update autoport to not generate it any more. Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber --- src/mainboard/sapphire/pureplatinumh61/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/sapphire/pureplatinumh61') diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index 95c59dfca3..aff01302b2 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -50,7 +50,6 @@ chip northbridge/intel/sandybridge register "gen2_dec" = "0x000c0a01" register "gen3_dec" = "0x00000000" register "gen4_dec" = "0x00000000" - register "p_cnt_throttling_supported" = "0" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" -- cgit v1.2.3