From ebf201b8f563ece11ceb60d81ba9cd676020da42 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 28 May 2019 13:51:36 +0200 Subject: sb/intel/bd82x6x: Use common final SPI OPs setup This also reworks the interface to override OPs from the devicetree to match the interface in sb/intel/common/spi. Change-Id: I534e989279d771ec4c0249af325bc3b30a661145 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33040 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/sapphire/pureplatinumh61/devicetree.cb | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src/mainboard/sapphire/pureplatinumh61') diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index aff01302b2..b863c30851 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -55,7 +55,14 @@ chip northbridge/intel/sandybridge register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" register "spi.opprefixes" = "{ 0x50, 0x06 }" - register "spi.ops" = "{ { 0, 1, 0x01 }, { 1, 1, 0x02 }, { 1, 0, 0x03 }, { 0, 0, 0x05 }, { 1, 1, 0x20 }, { 0, 0, 0x9f }, { 0, 1, 0xad }, { 0, 1, 0x04 } }" + register "spi.ops" = "{{0x01, WRITE_NO_ADDR}, + {0x02, WRITE_WITH_ADDR}, + {0x03, READ_WITH_ADDR}, + {0x05, READ_NO_ADDR}, + {0x20, WRITE_WITH_ADDR}, + {0x9f, READ_NO_ADDR}, + {0xad, WRITE_NO_ADDR}, + {0x04, WRITE_NO_ADDR}}" device pci 16.0 on # Management Engine Interface 1 subsystemid 0x174b 0x1007 end -- cgit v1.2.3