From 6beaef983aee5d886f6f8571855a92d608d98a17 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 16 Jun 2019 23:29:23 +0200 Subject: sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree Set up generic decode ranges based on the devicetree settings. Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Patrick Rudolph --- src/mainboard/sapphire/pureplatinumh61/romstage.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/mainboard/sapphire') diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c index 9a67ab295b..c7d8f0f724 100644 --- a/src/mainboard/sapphire/pureplatinumh61/romstage.c +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -24,10 +24,6 @@ void pch_enable_lpc(void) { pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0a01); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); } -- cgit v1.2.3