From 87f883959dee771d66e441e134111ba7b76b4ac5 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 6 Nov 2018 10:51:57 +0100 Subject: siemens/mc_apl3: Remove reduced clock rate for I2C0 There is no device on I2C0 which requires a lower clock rate. Change-Id: Ib9ad4d9026267d2079e95245994d84c163b28dbb Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/29504 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Paul Menzel --- src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'src/mainboard/siemens/mc_apl1') diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index 13ac4b5578..bb3bf6f2fa 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -46,18 +46,6 @@ chip soc/intel/apollolake # 0:HS400(Default), 1:HS200, 2:DDR50 register "emmc_host_max_speed" = "2" - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| I2C0 | Proximity Sensor | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .i2c[0] = { - .speed = I2C_SPEED_STANDARD - }, - }" - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 off end # - DPTF -- cgit v1.2.3