From beb0f2631fe6e49e86687cc3a7cf63ce41157a45 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Tue, 29 Apr 2014 13:09:50 +1000 Subject: superio/winbond/w83627hf: Avoid .c includes in mainboards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move towards the removal of the superio model specific xxx_serial_enable implementation. Make remaining superio romstage parts link-time symbols and fix corresponding mainboards to match. The following mainboards remain unconverted as they are ROMCC: - mainboard/supermicro/x6dai_g - mainboard/supermicro/x6dhe_g - mainboard/supermicro/x6dhr_ig - mainboard/supermicro/x6dhr_ig2 and so block the final removal of w83627hf_serial_enable(). Special cases: - mainboard/supermicro/h8qme_fam10: Provide local pnp_ sio func Provide local superio pnp_ programming entry/exit functions as to avoid making superio implementation global symbols. Although this is not the proper/final solution, it does mitigate possible symbol collisions and allow for continued superio refactorisation. Change-Id: Iaefb25d77512503050cb38313ca90855ebb538ad Signed-off-by: Edward O'Callaghan Reviewed-on: http://review.coreboot.org/5601 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/supermicro/h8qme_fam10/romstage.c | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) (limited to 'src/mainboard/supermicro/h8qme_fam10/romstage.c') diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index cca464c1f0..9898a25c0f 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -39,8 +39,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" -#include "superio/winbond/w83627hf/early_serial.c" -#include "superio/winbond/w83627hf/early_init.c" +#include +#include #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -114,6 +114,20 @@ static const u8 spd_addr[] = { #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3) +/* TODO: superio code should really not be in mainboard */ +static void pnp_enter_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); + outb(0x87, port); +} + +static void pnp_exit_ext_func_mode(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + static void write_GPIO(void) { pnp_enter_ext_func_mode(GPIO1_DEV); @@ -172,8 +186,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_set_clksel_48(DUMMY_DEV); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_set_clksel_48(DUMMY_DEV); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); write_GPIO(); -- cgit v1.2.3