From c02b4fc9db3c3c1e263027382697b566127f66bb Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 22 Mar 2010 11:42:32 +0000 Subject: printk_foo -> printk(BIOS_FOO, ...) Signed-off-by: Stefan Reinauer Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- .../supermicro/h8qme_fam10/get_bus_conf.c | 6 ++--- src/mainboard/supermicro/h8qme_fam10/irq_tables.c | 4 ++-- src/mainboard/supermicro/h8qme_fam10/mptable.c | 2 +- src/mainboard/supermicro/h8qme_fam10/romstage.c | 26 +++++++++++----------- 4 files changed, 19 insertions(+), 19 deletions(-) (limited to 'src/mainboard/supermicro/h8qme_fam10') diff --git a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c index effb614cf2..2ee436b9e7 100644 --- a/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c @@ -108,7 +108,7 @@ void get_bus_conf(void) m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); } for(i=2; i<8;i++) { @@ -117,7 +117,7 @@ void get_bus_conf(void) m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } else { - printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); } } @@ -143,7 +143,7 @@ void get_bus_conf(void) m->bus_type[j] = 1; if(m->bus_isa <= busn_max) m->bus_isa = busn_max + 1; - printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa); + printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa); } /*I/O APICs: APIC ID Version State Address*/ diff --git a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c index ec59d9ed86..26fcb4ace1 100644 --- a/src/mainboard/supermicro/h8qme_fam10/irq_tables.c +++ b/src/mainboard/supermicro/h8qme_fam10/irq_tables.c @@ -76,7 +76,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) addr &= ~15; /* This table must be between 0xf0000 & 0x100000 */ - printk_info("Writing IRQ routing tables to 0x%x...", addr); + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%x...", addr); pirq = (void *)(addr); v = (uint8_t *)(addr); @@ -131,7 +131,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->checksum = sum; } - printk_info("done.\n"); + printk(BIOS_INFO, "done.\n"); return (unsigned long) pirq_info; diff --git a/src/mainboard/supermicro/h8qme_fam10/mptable.c b/src/mainboard/supermicro/h8qme_fam10/mptable.c index edf7b7364f..fa59c9f498 100644 --- a/src/mainboard/supermicro/h8qme_fam10/mptable.c +++ b/src/mainboard/supermicro/h8qme_fam10/mptable.c @@ -146,7 +146,7 @@ void *smp_write_config_table(void *v) /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); - printk_debug("Wrote the mp table end at: %p - %p\n", + printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc)); return smp_next_mpe_entry(mc); } diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 45989aa5eb..ae20cdd53c 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -241,16 +241,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) uart_init(); console_init(); write_GPIO(); - printk_debug("\n"); + printk(BIOS_DEBUG, "\n"); /* Halt if there was a built in self test failure */ report_bist_failure(bist); val = cpuid_eax(1); - printk_debug("BSP Family_Model: %08x \n", val); - printk_debug("*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n"); - printk_debug("bsp_apicid = %02x \n", bsp_apicid); - printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "*sysinfo range: ["); print_debug_hex32((u32)sysinfo); print_debug(","); print_debug_hex32((u32)sysinfo+sizeof(struct sys_info)); print_debug("]\n"); + printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08x \n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -281,7 +281,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 /* Core0 on each node is configured. Now setup any additional cores. */ - printk_debug("start_other_cores()\n"); + printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); @@ -291,7 +291,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if FAM10_SET_FIDVID == 1 msr = rdmsr(0xc0010071); - printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only * need to be done once.*/ @@ -309,7 +309,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk_debug("End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); #endif wants_reset = mcp55_early_setup_x(); @@ -322,17 +322,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } if (wants_reset) - printk_debug("mcp55_early_setup_x wanted additional reset!\n"); + printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); post_code(0x3B); /* It's the time to set ctrl in sysinfo now; */ -printk_debug("fill_mem_ctrl()\n"); +printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x3D); -//printk_debug("enable_smbus()\n"); +//printk(BIOS_DEBUG, "enable_smbus()\n"); // enable_smbus(); /* enable in sio_setup */ post_code(0x3E); @@ -342,11 +342,11 @@ post_code(0x3E); post_code(0x40); - printk_debug("raminit_amdmct()\n"); + printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); -// printk_debug("\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); +// printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x42); // Should never see this post code. -- cgit v1.2.3