From 13f1c2af8be2cd7f7e99a678f5d428a65b771811 Mon Sep 17 00:00:00 2001 From: Yinghai Lu Date: Fri, 8 Jul 2005 02:49:49 +0000 Subject: eric patch 1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/supermicro/x6dhe_g2/irq_tables.c | 34 ++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 src/mainboard/supermicro/x6dhe_g2/irq_tables.c (limited to 'src/mainboard/supermicro/x6dhe_g2/irq_tables.c') diff --git a/src/mainboard/supermicro/x6dhe_g2/irq_tables.c b/src/mainboard/supermicro/x6dhe_g2/irq_tables.c new file mode 100644 index 0000000000..0851fbe3f8 --- /dev/null +++ b/src/mainboard/supermicro/x6dhe_g2/irq_tables.c @@ -0,0 +1,34 @@ +/* PCI: Interrupt Routing Table found at 0x4010f000 size = 176 */ + +#include + +const struct irq_routing_table intel_irq_routing_table = { + 0x52495024, /* u32 signature */ + 0x0100, /* u16 version */ + 272, /* u16 Table size 32+(15*devices) */ + 0x00, /* u8 Bus 0 */ + 0xf8, /* u8 Device 1, Function 0 */ + 0x0000, /* u16 reserve IRQ for PCI */ + 0x8086, /* u16 Vendor */ + 0x25a1, /* Device ID */ + 0x00000000, /* u32 miniport_data */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0xc4, /* u8 checksum - mod 256 checksum must give zero */ + { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x01<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x02<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x03<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x04<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x06<<3)|0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|0, {{0x60, 0xdcf8}, {0x63, 0xdcf8}, {0x62, 0xdc78}, {0x6b, 0xdcf8}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|1, {{0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|2, {{0x62, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1d<<3)|3, {{0x60, 0xdcf8}, {0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1f<<3)|0, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x00, (0x1f<<3)|1, {{0x62, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x04, (0x02<<3)|0, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x04, (0x02<<3)|1, {{0x62, 0xdc78}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, + {0x06, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x06, 0x00}, + {0x07, (0x02<<3)|0, {{0x60, 0xdc78}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x07, 0x00} + } +}; -- cgit v1.2.3