From 68241737044a9aade46346538729e9e3813551f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 10 Feb 2020 19:21:22 +0100 Subject: mainboard/supermicro: x11ssm-f: disable SUART3/4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SUART3/4 are unused on this board (verified by checking registers on vendor BMC firmware). Further they break the console for an unknown reason. Thus disable them. Change-Id: I30bb8184d03ee1037d9ec33eb1d93ee540563fc5 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/38818 Reviewed-by: Patrick Rudolph Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- .../x11-lga1151-series/variants/x11ssm-f/overridetree.cb | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) (limited to 'src/mainboard/supermicro') diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index ea90e0b0ba..0c7c17fffe 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -10,8 +10,6 @@ chip soc/intel/skylake register "gen1_dec" = "0x007c0a01" # Super IO SWC register "gen2_dec" = "0x000c0ca1" # IPMI KCS - register "gen3_dec" = "0x000c03e1" # UART3 - register "gen4_dec" = "0x000c02e1" # UART4 # PCIe configuration register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4 @@ -103,14 +101,8 @@ chip soc/intel/skylake end device pnp 2e.5 off end # KBC device pnp 2e.7 on end # GPIO - device pnp 2e.b on # SUART3 - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.c on # SUART4 - io 0x60 = 0x2e8 - irq 0x70 = 3 - end + device pnp 2e.b off end # SUART3 + device pnp 2e.c off end # SUART4 device pnp 2e.d on end # iLPC2AHB device pnp 2e.e on # Mailbox io 0x60 = 0xa40 -- cgit v1.2.3