From 11f054a5785af6a1c29eebbe1b91f3570dca6228 Mon Sep 17 00:00:00 2001 From: Carl-Daniel Hailfinger Date: Fri, 3 Apr 2009 12:55:55 +0000 Subject: Next step. Kill auto.c and failover.c and clean up Config.lb for tyan/s2735 tyan/s2850 tyan/s2875 tyan/s2880 tyan/s2881 tyan/s2882 tyan/s2885 tyan/s2891 tyan/s2892 tyan/s2895 Abuild log is completely identical with and without the patch. Signed-off-by: Carl-Daniel Hailfinger Acked-by: Stefan Reinauer Acked-by: Patrick Georgi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/tyan/s2892/auto.c | 153 ------------------------------------ src/mainboard/tyan/s2892/failover.c | 90 --------------------- 2 files changed, 243 deletions(-) delete mode 100644 src/mainboard/tyan/s2892/auto.c delete mode 100644 src/mainboard/tyan/s2892/failover.c (limited to 'src/mainboard/tyan/s2892') diff --git a/src/mainboard/tyan/s2892/auto.c b/src/mainboard/tyan/s2892/auto.c deleted file mode 100644 index bce2bbda4d..0000000000 --- a/src/mainboard/tyan/s2892/auto.c +++ /dev/null @@ -1,153 +0,0 @@ -#define ASSEMBLY 1 - -#include -#include -#include -#include -#include -#include -#include -#include "option_table.h" -#include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "ram/ramtest.c" - -#define K8_HT_FREQ_1G_SUPPORT 1 -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/ck804_early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" -#include "cpu/amd/model_fxx/apic_timer.c" -#include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" -#include "superio/winbond/w83627hf/w83627hf_early_serial.c" - -#include "cpu/amd/mtrr/amd_earlymtrr.c" -#include "cpu/x86/bist.h" -#include "cpu/amd/dualcore/dualcore.c" - -#include "northbridge/amd/amdk8/setup_resource_map.c" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -static void hard_reset(void) -{ - set_bios_reset(); - - /* full reset */ - outb(0x0a, 0x0cf9); - outb(0x0e, 0x0cf9); -} - -static void soft_reset(void) -{ - set_bios_reset(); -#if 1 - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -#endif -} - -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#define QRANK_DIMM_SUPPORT 1 -#include "northbridge/amd/amdk8/raminit.c" -#include "northbridge/amd/amdk8/coherent_ht.c" -#include "sdram/generic_sdram.c" - -/* tyan does not want the default */ -#include "resourcemap.c" - -#define FIRST_CPU 1 -#define SECOND_CPU 1 -#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) - -#define CK804_NUM 1 -#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" -//set GPIO to input mode -#define CK804_MB_SETUP \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ - RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ - -#include "southbridge/nvidia/ck804/ck804_early_setup.c" - -static void main(unsigned long bist) -{ - static const struct mem_controller cpu[] = { -#if FIRST_CPU - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x18, 0), - .f1 = PCI_DEV(0, 0x18, 1), - .f2 = PCI_DEV(0, 0x18, 2), - .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, - .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, - }, -#endif -#if SECOND_CPU - { - .node_id = 1, - .f0 = PCI_DEV(0, 0x19, 0), - .f1 = PCI_DEV(0, 0x19, 1), - .f2 = PCI_DEV(0, 0x19, 2), - .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, - .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, - }, -#endif - }; - - int needs_reset; - - if (bist == 0) { - k8_init_and_stop_secondaries(); - } - - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); - uart_init(); - console_init(); - - /* Halt if there was a built in self test failure */ -// report_bist_failure(bist); - - setup_s2892_resource_map(); - - needs_reset = setup_coherent_ht_domain(); - - needs_reset |= ht_setup_chains_x(); - - needs_reset |= ck804_early_setup_x(); - - if (needs_reset) { - print_info("ht reset -\r\n"); - soft_reset(); - } - - enable_smbus(); - - memreset_setup(); - sdram_initialize(ARRAY_SIZE(cpu), cpu); - -} diff --git a/src/mainboard/tyan/s2892/failover.c b/src/mainboard/tyan/s2892/failover.c deleted file mode 100644 index 2d90e37cdd..0000000000 --- a/src/mainboard/tyan/s2892/failover.c +++ /dev/null @@ -1,90 +0,0 @@ -#define ASSEMBLY 1 -#include -#include -#include -#include -#include -#include -#include "pc80/mc146818rtc_early.c" - -#include "southbridge/nvidia/ck804/ck804_enable_rom.c" -#include "northbridge/amd/amdk8/early_ht.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "northbridge/amd/amdk8/reset_test.c" - -static void sio_setup(void) -{ - - unsigned value; - uint32_t dword; - uint8_t byte; - - byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); - - dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); - pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); - - -} - -#if CONFIG_LOGICAL_CPUS==1 -#include "cpu/amd/dualcore/dualcore_id.c" -#endif - -static unsigned long main(unsigned long bist) -{ - /* Make cerain my local apic is useable */ - enable_lapic(); - - /* Is this a cpu only reset? */ - if (early_mtrr_init_detected()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Is this a secondary cpu? */ - if (!boot_cpu()) { - if (last_boot_normal()) { - goto normal_image; - } else { - goto fallback_image; - } - } - - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - - sio_setup(); - - /* Setup the ck804 */ - ck804_enable_rom(); - - /* Is this a deliberate reset by the bios */ - if (bios_reset_detected() && last_boot_normal()) { - goto normal_image; - } - /* This is the primary cpu how should I boot? */ - else if (do_normal_boot()) { - goto normal_image; - } - else { - goto fallback_image; - } - normal_image: - asm volatile ("jmp __normal_image" - : /* outputs */ - : "a" (bist) /* inputs */ - : /* clobbers */ - ); - fallback_image: - return bist; -} -- cgit v1.2.3