From 5726f92027c4299a7cad46c9153dbe55543efb5e Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 8 Oct 2009 07:43:09 +0000 Subject: Kconfig: AMD Fam10, all Tyan boards. Fam10 doesn't build due to size constraints at this time. Signed-off-by: Patrick Georgi Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/tyan/s2912_fam10/Kconfig | 162 ++++++++++++++++++++++++++++ src/mainboard/tyan/s2912_fam10/Makefile.inc | 66 ++++++++++++ 2 files changed, 228 insertions(+) create mode 100644 src/mainboard/tyan/s2912_fam10/Kconfig create mode 100644 src/mainboard/tyan/s2912_fam10/Makefile.inc (limited to 'src/mainboard/tyan/s2912_fam10') diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig new file mode 100644 index 0000000000..9b1eb2a7fa --- /dev/null +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -0,0 +1,162 @@ + +config BOARD_TYAN_S2912_FAM10 + bool "S2912_FAM10" + select ARCH_X86 + select CPU_AMD_K8 + select CPU_AMD_SOCKET_F_1207 + select NORTHBRIDGE_AMD_AMDFAM10 + select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX + select SOUTHBRIDGE_NVIDIA_MCP55 + select SUPERIO_WINBOND_W83627HF + select PIRQ_TABLE + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select IOAPIC + select MEM_TRAIN_SEQ + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + +config MAINBOARD_DIR + string + default tyan/s2912_fam10 + depends on BOARD_TYAN_S2912_FAM10 + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_TYAN_S2912_FAM10 + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_TYAN_S2912_FAM10 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_TYAN_S2912_FAM10 + +config APIC_ID_OFFSET + hex + default 16 + depends on BOARD_TYAN_S2912_FAM10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 2 + depends on BOARD_TYAN_S2912_FAM10 + +config LB_CKS_RANGE_START + int + default 49 + depends on BOARD_TYAN_S2912_FAM10 + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_TYAN_S2912_FAM10 + +config LB_CKS_LOC + int + default 123 + depends on BOARD_TYAN_S2912_FAM10 + +config MAINBOARD_PART_NUMBER + string + default "S2912 (Fam10)" + depends on BOARD_TYAN_S2912_FAM10 + +config PCI_64BIT_PREF_MEM + bool + default n + depends on BOARD_TYAN_S2912_FAM10 + +config HAVE_FALLBACK_BOOT + bool + default n + depends on BOARD_TYAN_S2912_FAM10 + +config USE_FALLBACK_IMAGE + bool + default n + depends on BOARD_TYAN_S2912_FAM10 + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_TYAN_S2912_FAM10 + +config MAX_CPUS + int + default 2 + depends on BOARD_TYAN_S2912_FAM10 + +config MAX_PHYSICAL_CPUS + int + default 1 + depends on BOARD_TYAN_S2912_FAM10 + +config AP_CODE_IN_CAR + bool + default n + depends on BOARD_TYAN_S2912_FAM10 + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_TYAN_S2912_FAM10 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_TYAN_S2912_FAM10 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x0 + depends on BOARD_TYAN_S2912_FAM10 + +config USE_INIT + bool + default n + depends on BOARD_TYAN_S2912_FAM10 + +config SERIAL_CPU_INIT + bool + default n + depends on BOARD_TYAN_S2912_FAM10 + +config WAIT_BEFORE_CPUS_INIT + bool + default n + depends on BOARD_TYAN_S2912_FAM10 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x10f1 + depends on BOARD_TYAN_S2912_FAM10 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x2912 + depends on BOARD_TYAN_S2912_FAM10 + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_TYAN_S2912_FAM10 + +config AMD_UCODE_PATCH_FILE + string + default "mc_patch_01000095.h" + depends on BOARD_TYAN_S2912_FAM10 + +config ENABLE_APIC_EXT_ID + bool + default y + depends on BOARD_TYAN_S2912_FAM10 + +config AMDMCT + bool + default y + depends on BOARD_TYAN_S2912_FAM10 diff --git a/src/mainboard/tyan/s2912_fam10/Makefile.inc b/src/mainboard/tyan/s2912_fam10/Makefile.inc new file mode 100644 index 0000000000..83271c2a4c --- /dev/null +++ b/src/mainboard/tyan/s2912_fam10/Makefile.inc @@ -0,0 +1,66 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +driver-y += mainboard.o + +#needed by irq_tables and mptable and acpi_tables +obj-y += get_bus_conf.o +obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o +obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o +obj-$(CONFIG_USE_INIT) += cache_as_ram_auto.o +obj-$(CONFIG_AP_CODE_IN_CAR) += apc_auto.o + +# This is part of the conversion to init-obj and away from included code. +initobj-y += crt0.o +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/southbridge/nvidia/mcp55/id.inc +crt0-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.inc +crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc +crt0-y += auto.inc + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/southbridge/nvidia/mcp55/id.lds +ldscript-y += ../../../../src/southbridge/nvidia/mcp55/romstrap.lds +ldscript-y += ../../../../src/arch/i386/lib/failover.lds +ldscript-$(CONFIG_AP_CODE_IN_CAR) += ../../../../src/arch/i386/init/ldscript_apc.lb + +ifdef POST_EVALUATION + +$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + iasl -p $(obj)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl + mv $(obj)/dsdt.hex $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/apc_auto.o: $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/apc_auto.c -o $@ + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ + perl -e 's/\.rodata/.rom.data/g' -pi $@ + perl -e 's/\.text/.section .rom.text/g' -pi $@ + +endif -- cgit v1.2.3