From 0c797f1c28cd16c64482b2cea554e89baaa31445 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 21 Jul 2014 19:35:16 +0300 Subject: AGESA: Drop offset on PCI device enumeration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Integrated PCI devices in southbridge silicon have static BDFs, no need to have variables to store the parent bus or an offset with constant zero. Change-Id: I37d3794d36b5e5775da9215574ddc199696646d0 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/6333 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi --- src/mainboard/tyan/s8226/mptable.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/mainboard/tyan/s8226/mptable.c') diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c index 6a12f2b821..3793212711 100644 --- a/src/mainboard/tyan/s8226/mptable.c +++ b/src/mainboard/tyan/s8226/mptable.c @@ -29,8 +29,6 @@ #include extern u8 bus_sp5100[2]; -extern u32 sbdn_sr5650; -extern u32 sbdn_sp5100; static void *smp_write_config_table(void *v) { @@ -60,7 +58,7 @@ static void *smp_write_config_table(void *v) apicid_sp5100 = CONFIG_MAX_CPUS + 1; apicid_sr5650 = apicid_sp5100 + 1; - dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); if (dev) { /* Set SP5100 IOAPIC ID */ dword = pci_read_config32(dev, 0x74) & 0xfffffff0; -- cgit v1.2.3