From 38f147ed3d9fdd6bfb23d7226f6fdd3fc5db53d0 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 8 Feb 2010 12:20:50 +0000 Subject: janitor task: unify and cleanup naming. cache_as_ram_auto.c and auto.c are both called "romstage.c" now. Signed-off-by: Stefan Reinauer Acked-by: Patrick Georgi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/via/epia-m/Makefile.inc | 6 +- src/mainboard/via/epia-m/auto.c | 154 ---------------------------------- src/mainboard/via/epia-m/romstage.c | 154 ++++++++++++++++++++++++++++++++++ 3 files changed, 157 insertions(+), 157 deletions(-) delete mode 100644 src/mainboard/via/epia-m/auto.c create mode 100644 src/mainboard/via/epia-m/romstage.c (limited to 'src/mainboard/via/epia-m') diff --git a/src/mainboard/via/epia-m/Makefile.inc b/src/mainboard/via/epia-m/Makefile.inc index 95364b5a5a..3c82c8513d 100644 --- a/src/mainboard/via/epia-m/Makefile.inc +++ b/src/mainboard/via/epia-m/Makefile.inc @@ -41,7 +41,7 @@ crt0s += $(src)/cpu/x86/16bit/reset16.inc crt0s += $(src)/northbridge/via/vx800/romstrap.inc crt0s += $(src)/arch/i386/lib/id.inc crt0s += $(src)/cpu/x86/fpu_enable.inc -crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc +crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc crt0s += $(src)/cpu/x86/mmx_disable.inc ifdef POST_EVALUATION @@ -53,8 +53,8 @@ $(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl mv dsdt.hex $@ -$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h - $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ +$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/option_table.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@ perl -e 's/\.rodata/.rom.data/g' -pi $@ perl -e 's/\.text/.section .rom.text/g' -pi $@ diff --git a/src/mainboard/via/epia-m/auto.c b/src/mainboard/via/epia-m/auto.c deleted file mode 100644 index 77cac78bd3..0000000000 --- a/src/mainboard/via/epia-m/auto.c +++ /dev/null @@ -1,154 +0,0 @@ -#define ASSEMBLY 1 -#define __PRE_RAM__ - -#include -#include -#include -#if 0 -#include -#endif -#include -#include -#include -#include -#include -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "lib/ramtest.c" -#include "northbridge/via/vt8623/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "cpu/x86/bist.h" -#include "pc80/udelay_io.c" -#include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "lib/debug.c" -#include "southbridge/via/vt8235/vt8235_early_smbus.c" -#include "southbridge/via/vt8235/vt8235_early_serial.c" - -static void memreset_setup(void) -{ -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/via/vt8623/raminit.c" - -static void enable_mainboard_devices(void) -{ - device_t dev; - - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_8235), 0); - - if (dev == PCI_DEV_INVALID) { - die("Southbridge not found!!!\n"); - } - pci_write_config8(dev, 0x50, 0x80); - pci_write_config8(dev, 0x51, 0x1f); -#if 0 - // This early setup switches IDE into compatibility mode before PCI gets - // a chance to assign I/Os - // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax - // // movb $0x09, %dl - // movb $0x00, %dl - // PCI_WRITE_CONFIG_BYTE -#endif - /* we do this here as in V2, we can not yet do raw operations - * to pci! - */ - dev += 0x100; /* ICKY */ - - pci_write_config8(dev, 0x04, 7); - pci_write_config8(dev, 0x40, 3); - pci_write_config8(dev, 0x42, 0); - pci_write_config8(dev, 0x3c, 0xe); - pci_write_config8(dev, 0x3d, 0); -} - -static void enable_shadow_ram(void) -{ - device_t dev = 0; /* no need to look up 0:0.0 */ - unsigned char shadowreg; - /* dev 0 for southbridge */ - shadowreg = pci_read_config8(dev, 0x63); - /* 0xf0000-0xfffff */ - shadowreg |= 0x30; - pci_write_config8(dev, 0x63, shadowreg); -} - -static void main(unsigned long bist) -{ - unsigned long x; - device_t dev; - - /* - * Enable VGA; 32MB buffer. - */ - pci_write_config8(0, 0xe1, 0xdd); - - /* - * Disable the firewire stuff, which apparently steps on IO 0+ on - * reset. Doh! - */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_6305), 0); - if (dev != PCI_DEV_INVALID) { - pci_write_config8(dev, 0x15, 0x1c); - } - - enable_vt8235_serial(); - uart_init(); - console_init(); - - enable_smbus(); - - print_spew("In auto.c:main()\r\n"); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - // init_timer(); - - outb(5, 0x80); - - print_debug(" Enabling mainboard devices\r\n"); - enable_mainboard_devices(); - - print_debug(" Enabling shadow ram\r\n"); - enable_shadow_ram(); - - ddr_ram_setup((const struct mem_controller *)0); - - /* Check all of memory */ -#if 0 - ram_check(0x00000000, msr.lo); -#endif -#if 0 - static const struct { - unsigned long lo, hi; - } check_addrs[] = { - /* Check 16MB of memory @ 0*/ - { 0x00000000, 0x01000000 }, -#if TOTAL_CPUS > 1 - /* Check 16MB of memory @ 2GB */ - { 0x80000000, 0x81000000 }, -#endif - }; - int i; - for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { - ram_check(check_addrs[i].lo, check_addrs[i].hi); - } -#endif - - if (bist == 0) { - print_debug(" Doing MTRR init.\r\n"); - early_mtrr_init(); - } - - //dump_pci_devices(); - - print_spew("Leaving auto.c:main()\r\n"); -} diff --git a/src/mainboard/via/epia-m/romstage.c b/src/mainboard/via/epia-m/romstage.c new file mode 100644 index 0000000000..8b8a96aa93 --- /dev/null +++ b/src/mainboard/via/epia-m/romstage.c @@ -0,0 +1,154 @@ +#define ASSEMBLY 1 +#define __PRE_RAM__ + +#include +#include +#include +#if 0 +#include +#endif +#include +#include +#include +#include +#include +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "lib/ramtest.c" +#include "northbridge/via/vt8623/raminit.h" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "lib/debug.c" +#include "southbridge/via/vt8235/vt8235_early_smbus.c" +#include "southbridge/via/vt8235/vt8235_early_serial.c" + +static void memreset_setup(void) +{ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/via/vt8623/raminit.c" + +static void enable_mainboard_devices(void) +{ + device_t dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_8235), 0); + + if (dev == PCI_DEV_INVALID) { + die("Southbridge not found!!!\n"); + } + pci_write_config8(dev, 0x50, 0x80); + pci_write_config8(dev, 0x51, 0x1f); +#if 0 + // This early setup switches IDE into compatibility mode before PCI gets + // a chance to assign I/Os + // movl $CONFIG_ADDR(0, 0x89, 0x42), %eax + // // movb $0x09, %dl + // movb $0x00, %dl + // PCI_WRITE_CONFIG_BYTE +#endif + /* we do this here as in V2, we can not yet do raw operations + * to pci! + */ + dev += 0x100; /* ICKY */ + + pci_write_config8(dev, 0x04, 7); + pci_write_config8(dev, 0x40, 3); + pci_write_config8(dev, 0x42, 0); + pci_write_config8(dev, 0x3c, 0xe); + pci_write_config8(dev, 0x3d, 0); +} + +static void enable_shadow_ram(void) +{ + device_t dev = 0; /* no need to look up 0:0.0 */ + unsigned char shadowreg; + /* dev 0 for southbridge */ + shadowreg = pci_read_config8(dev, 0x63); + /* 0xf0000-0xfffff */ + shadowreg |= 0x30; + pci_write_config8(dev, 0x63, shadowreg); +} + +static void main(unsigned long bist) +{ + unsigned long x; + device_t dev; + + /* + * Enable VGA; 32MB buffer. + */ + pci_write_config8(0, 0xe1, 0xdd); + + /* + * Disable the firewire stuff, which apparently steps on IO 0+ on + * reset. Doh! + */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_6305), 0); + if (dev != PCI_DEV_INVALID) { + pci_write_config8(dev, 0x15, 0x1c); + } + + enable_vt8235_serial(); + uart_init(); + console_init(); + + enable_smbus(); + + print_spew("In romstage.c:main()\r\n"); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + // init_timer(); + + outb(5, 0x80); + + print_debug(" Enabling mainboard devices\r\n"); + enable_mainboard_devices(); + + print_debug(" Enabling shadow ram\r\n"); + enable_shadow_ram(); + + ddr_ram_setup((const struct mem_controller *)0); + + /* Check all of memory */ +#if 0 + ram_check(0x00000000, msr.lo); +#endif +#if 0 + static const struct { + unsigned long lo, hi; + } check_addrs[] = { + /* Check 16MB of memory @ 0*/ + { 0x00000000, 0x01000000 }, +#if TOTAL_CPUS > 1 + /* Check 16MB of memory @ 2GB */ + { 0x80000000, 0x81000000 }, +#endif + }; + int i; + for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { + ram_check(check_addrs[i].lo, check_addrs[i].hi); + } +#endif + + if (bist == 0) { + print_debug(" Doing MTRR init.\r\n"); + early_mtrr_init(); + } + + //dump_pci_devices(); + + print_spew("Leaving romstage.c:main()\r\n"); +} -- cgit v1.2.3