From 5276941c8b9a3294fda4eb5d102c8333688d29a5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 17 Jun 2016 07:55:03 +0300 Subject: AMD boards: Fix romstage main() declaration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Boards incorrectly used intel include file for AMD board. Change-Id: I6d3172d1aa5c91c989a6ef63066a7cd6f70013f5 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15232 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/via/epia-cn/romstage.c | 2 +- src/mainboard/via/epia-m700/romstage.c | 2 +- src/mainboard/via/epia-m850/romstage.c | 2 +- src/mainboard/via/pc2500e/romstage.c | 2 +- src/mainboard/via/vt8454c/romstage.c | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'src/mainboard/via') diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index b71fe1cebc..a28bf784a2 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include "southbridge/via/vt8237r/early_smbus.c" #include "southbridge/via/vt8237r/early_serial.c" @@ -73,7 +74,6 @@ static const struct mem_controller ctrl = { .channel0 = { DIMM0 }, }; -#include void main(unsigned long bist) { /* Enable multifunction for northbridge. */ diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 6878623300..9f2c14e3bf 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include /* This file contains the board-special SI value for raminit.c. */ @@ -365,7 +366,6 @@ static void EmbedComInit(void) #endif /* cache_as_ram.inc jumps to here. */ -#include void main(unsigned long bist) { u16 boot_mode; diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index d40fd6910c..f3f0ec6e9d 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -37,7 +38,6 @@ #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) /* cache_as_ram.inc jumps to here. */ -#include void main(unsigned long bist) { u32 tolm; diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 17efa3812c..7d12e872d2 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include "southbridge/via/vt8237r/early_smbus.c" #include @@ -49,7 +50,6 @@ static const struct mem_controller ctrl = { .channel0 = { DIMM0 }, /* TODO: CN700 currently only supports 1 DIMM. */ }; -#include void main(unsigned long bist) { /* Enable multifunction for northbridge. */ diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index f93b09a5e5..d2af46c5c8 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include "northbridge/via/cx700/early_smbus.c" #include "lib/debug.c" @@ -76,7 +77,6 @@ static void enable_shadow_ram(const struct mem_controller *ctrl) pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg); } -#include void main(unsigned long bist) { /* Set statically so it should work with cx700 as well */ -- cgit v1.2.3