From 06cfb21e243ec74660e4886cef2f2e9c6c755d9e Mon Sep 17 00:00:00 2001 From: Roy Mingi Park Date: Mon, 3 Jun 2019 16:11:25 -0700 Subject: mb/google/sarien: Fix SSD's power off sequence before going to S5 BUG=b:133389422 TEST=check SSD's power off sequence to meet PCIE requirement. SSD's reset should be cleared before clearing SSD's power EN Pin. Change-Id: Ia106b805deafb8a442b56bcce91b51135cb32988 Signed-off-by: Roy Mingi Park Reviewed-on: https://review.coreboot.org/c/coreboot/+/33182 Reviewed-by: EricR Lai Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- .../google/sarien/variants/arcada/include/variant/acpi/mainboard.asl | 3 ++- .../google/sarien/variants/sarien/include/variant/acpi/mainboard.asl | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl index 6eba2bcb21..4b05ba8e90 100644 --- a/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl @@ -40,8 +40,9 @@ Method (MPTS, 1) /* Clear SSD EN adn RST pin to avoid leakage */ If (Arg0 == 5) { - \_SB.PCI0.CTXS (SSD_EN) \_SB.PCI0.CTXS (SSD_RST) + Sleep(1) + \_SB.PCI0.CTXS (SSD_EN) } } diff --git a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl index 6eba2bcb21..4b05ba8e90 100644 --- a/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl +++ b/src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl @@ -40,8 +40,9 @@ Method (MPTS, 1) /* Clear SSD EN adn RST pin to avoid leakage */ If (Arg0 == 5) { - \_SB.PCI0.CTXS (SSD_EN) \_SB.PCI0.CTXS (SSD_RST) + Sleep(1) + \_SB.PCI0.CTXS (SSD_EN) } } -- cgit v1.2.3