From 075fbe820127c454a6854b87c277a2ca30dee1c2 Mon Sep 17 00:00:00 2001 From: Myles Watson Date: Thu, 15 Apr 2010 05:19:29 +0000 Subject: Remove a few more warnings from fam10. Signed-off-by: Myles Watson Acked-by: Myles Watson git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5440 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/mahogany_fam10/romstage.c | 4 ++-- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 4 ++-- src/mainboard/msi/ms9652_fam10/romstage.c | 4 ++-- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 4 ++-- src/mainboard/supermicro/h8qme_fam10/romstage.c | 4 ++-- src/mainboard/tyan/s2912_fam10/romstage.c | 6 ++---- 6 files changed, 12 insertions(+), 14 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 1f5366912d..17a0fd606f 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -93,6 +93,8 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -100,8 +102,6 @@ static int spd_read_byte(u32 device, u32 address) #include "southbridge/amd/sb700/sb700_early_setup.c" //#include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" #define RC00 0 #define RC01 1 diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 316e257dc1..b571d37c40 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -115,6 +115,8 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -122,8 +124,6 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" #include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 4a3e9f4c95..0d2f80fcf8 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -118,6 +118,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -140,8 +142,6 @@ static void sio_setup(void) } #include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index a60a4a610a..a763414a4e 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -107,6 +107,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -137,8 +139,6 @@ static void sio_setup(void) } #include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index e17614bbf1..1b2686dbda 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -111,6 +111,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -141,8 +143,6 @@ static void sio_setup(void) } #include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1) #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 128f3b3f49..5f6d2a7691 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -113,10 +113,10 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" - - #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -144,8 +144,6 @@ static void sio_setup(void) } #include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -- cgit v1.2.3