From 0c89ed93d758d3abd82f19abf12fa66c16610a57 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 17 May 2019 14:50:48 +0530 Subject: mb/google/{arcada, hatch, sarien}: Override FSP default GPIO PM configuration sarien/arcada: GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D18 IRQ mapped for H1 TPM. hatch: GPIO_COMM_0/1/2/3: Enable gpio community all PM configuration GPIO_COMM_4: Disable RCOMP clock gating due to GPP_C21 IRQ mapped for H1 TPM. BUG=b:130764684 TEST=H1 TPM interrupt working find and able to boot from fixed boot media Change-Id: Ia4d5483847a4d243b9038119d4bb5990591cc754 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/32848 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 10 ++++++++++ src/mainboard/google/sarien/variants/arcada/devicetree.cb | 10 ++++++++++ src/mainboard/google/sarien/variants/sarien/devicetree.cb | 10 ++++++++++ 3 files changed, 30 insertions(+) (limited to 'src/mainboard') diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 09e004e84c..9d10cac41b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -89,6 +89,16 @@ chip soc/intel/cannonlake register "PchHdaAudioLinkSsp1" = "1" register "PchHdaAudioLinkDmic0" = "1" + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index b6377ba55d..d3848a24b0 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -201,6 +201,16 @@ chip soc/intel/cannonlake register "PcieClkSrcUsage[4]" = "12" register "PcieClkSrcClkReq[4]" = "4" + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 3807047e0f..c96423c93d 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -205,6 +205,16 @@ chip soc/intel/cannonlake register "PcieClkSrcUsage[2]" = "12" register "PcieClkSrcClkReq[2]" = "2" + # GPIO PM programming + register "gpio_override_pm" = "1" + + # GPIO community PM configuration + register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN" + register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG" + device cpu_cluster 0 on device lapic 0 on end end -- cgit v1.2.3