From 0f61a4fc98f135c0ed22c67ee3241bf5670a61e2 Mon Sep 17 00:00:00 2001 From: Myles Watson Date: Fri, 16 Oct 2009 16:32:57 +0000 Subject: Change CONFIG_LB_MEM_TOPK to CONFIG_RAMTOP to match CONFIG_RAMBASE. Signed-off-by: Myles Watson Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/serengeti_cheetah/Options.lb | 4 ++-- src/mainboard/amd/serengeti_cheetah/apc_auto.c | 2 +- src/mainboard/amd/serengeti_cheetah_fam10/Kconfig | 4 ++-- src/mainboard/amd/serengeti_cheetah_fam10/Options.lb | 4 ++-- src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c | 2 +- src/mainboard/asus/a8n_e/Options.lb | 1 - src/mainboard/asus/a8v-e_se/Options.lb | 4 ++-- src/mainboard/asus/m2v-mx_se/Options.lb | 4 ++-- src/mainboard/asus/m2v-mx_se/mainboard.c | 2 +- src/mainboard/gigabyte/ga_2761gxdk/Options.lb | 4 ++-- src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c | 2 +- src/mainboard/gigabyte/m57sli/Options.lb | 4 ++-- src/mainboard/gigabyte/m57sli/apc_auto.c | 2 +- src/mainboard/hp/dl145_g3/Options.lb | 4 ++-- src/mainboard/intel/truxton/Options.lb | 6 +++--- src/mainboard/iwill/dk8_htx/Options.lb | 4 ++-- src/mainboard/msi/ms7135/Options.lb | 3 --- src/mainboard/msi/ms7260/Options.lb | 4 ++-- src/mainboard/msi/ms7260/apc_auto.c | 2 +- src/mainboard/msi/ms9185/Options.lb | 4 ++-- src/mainboard/nvidia/l1_2pvv/Options.lb | 4 ++-- src/mainboard/nvidia/l1_2pvv/apc_auto.c | 2 +- src/mainboard/supermicro/h8dme/Options.lb | 4 ++-- src/mainboard/supermicro/h8dme/apc_auto.c | 2 +- src/mainboard/supermicro/h8dmr/Options.lb | 4 ++-- src/mainboard/supermicro/h8dmr/apc_auto.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/Options.lb | 4 ++-- src/mainboard/supermicro/h8dmr_fam10/apc_auto.c | 2 +- src/mainboard/tyan/s2885/Options.lb | 2 -- src/mainboard/tyan/s2891/Options.lb | 2 -- src/mainboard/tyan/s2892/Options.lb | 2 -- src/mainboard/tyan/s2895/Options.lb | 4 ++-- src/mainboard/tyan/s2912/Options.lb | 4 ++-- src/mainboard/tyan/s2912/apc_auto.c | 2 +- src/mainboard/tyan/s2912_fam10/Options.lb | 4 ++-- src/mainboard/tyan/s2912_fam10/apc_auto.c | 2 +- src/mainboard/via/epia-n/Options.lb | 4 ++-- 37 files changed, 53 insertions(+), 63 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/amd/serengeti_cheetah/Options.lb b/src/mainboard/amd/serengeti_cheetah/Options.lb index dc57febc81..a20289d794 100644 --- a/src/mainboard/amd/serengeti_cheetah/Options.lb +++ b/src/mainboard/amd/serengeti_cheetah/Options.lb @@ -80,7 +80,7 @@ uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -107,7 +107,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot diff --git a/src/mainboard/amd/serengeti_cheetah/apc_auto.c b/src/mainboard/amd/serengeti_cheetah/apc_auto.c index 5a173e006b..c8723e6fbf 100644 --- a/src/mainboard/amd/serengeti_cheetah/apc_auto.c +++ b/src/mainboard/amd/serengeti_cheetah/apc_auto.c @@ -75,7 +75,7 @@ static inline unsigned get_nodes(void) void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig index df024f5c2b..8d59b6ca11 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig @@ -95,9 +95,9 @@ config AMD_UCODE_PATCH_FILE default "mc_patch_01000095.h" depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 -config LB_MEM_TOPK +config RAMTOP hex - default 0x4000 + default 0x1000000 depends on BOARD_AMD_SERENGETI_CHEETAH_FAM10 config HEAP_SIZE diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb index a5ba422069..2d82dfde4e 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb @@ -98,7 +98,7 @@ uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_PCI_BUS_SEGN_BITS @@ -135,7 +135,7 @@ default CONFIG_FAILOVER_SIZE=0x02000 #more 1M for pgtbl #if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time. -default CONFIG_LB_MEM_TOPK=16384 +default CONFIG_RAMTOP=16384*1024 ## ## Build code for the fallback boot diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c b/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c index fbb8c14388..69e3ffbb9d 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c @@ -74,7 +74,7 @@ void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/asus/a8n_e/Options.lb b/src/mainboard/asus/a8n_e/Options.lb index 50a15848a8..02d4407739 100644 --- a/src/mainboard/asus/a8n_e/Options.lb +++ b/src/mainboard/asus/a8n_e/Options.lb @@ -93,7 +93,6 @@ uses CONFIG_HT_CHAIN_UNITID_BASE uses CONFIG_HT_CHAIN_END_UNITID_BASE uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_LB_MEM_TOPK uses CONFIG_USE_PRINTK_IN_CAR default CONFIG_ROM_SIZE = 512 * 1024 diff --git a/src/mainboard/asus/a8v-e_se/Options.lb b/src/mainboard/asus/a8v-e_se/Options.lb index bdf0972612..92c51feb0c 100644 --- a/src/mainboard/asus/a8v-e_se/Options.lb +++ b/src/mainboard/asus/a8v-e_se/Options.lb @@ -41,7 +41,7 @@ uses CONFIG_XIP_ROM_BASE uses CONFIG_STACK_SIZE uses CONFIG_HEAP_SIZE # uses CONFIG_USE_OPTION_TABLE -# uses CONFIG_LB_MEM_TOPK +# uses CONFIG_RAMTOP uses CONFIG_GENERATE_ACPI_TABLES uses CONFIG_HAVE_ACPI_RESUME uses CONFIG_LB_CKS_RANGE_START @@ -147,7 +147,7 @@ default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 256 * 1024 # More 1M for pgtbl. -# default CONFIG_LB_MEM_TOPK = 2048 +# default CONFIG_RAMTOP = 2048*1024 default CONFIG_RAMBASE = 0x00004000 # default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE default CONFIG_ROM_PAYLOAD = 1 diff --git a/src/mainboard/asus/m2v-mx_se/Options.lb b/src/mainboard/asus/m2v-mx_se/Options.lb index 94e57f941b..eaa7168682 100644 --- a/src/mainboard/asus/m2v-mx_se/Options.lb +++ b/src/mainboard/asus/m2v-mx_se/Options.lb @@ -41,7 +41,7 @@ uses CONFIG_XIP_ROM_BASE uses CONFIG_STACK_SIZE uses CONFIG_HEAP_SIZE uses CONFIG_USE_OPTION_TABLE -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_GENERATE_ACPI_TABLES uses CONFIG_HAVE_MAINBOARD_RESOURCES uses CONFIG_HAVE_ACPI_RESUME @@ -151,7 +151,7 @@ default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043 default CONFIG_STACK_SIZE = 8 * 1024 default CONFIG_HEAP_SIZE = 256 * 1024 # More 1M for pgtbl. -default CONFIG_LB_MEM_TOPK = 32768 +default CONFIG_RAMTOP = 32768*1024 # to 1MB default CONFIG_RAMBASE = 0x1F00000 default CONFIG_USE_OPTION_TABLE = 0 diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c index d25a8edf04..fd8103c729 100644 --- a/src/mainboard/asus/m2v-mx_se/mainboard.c +++ b/src/mainboard/asus/m2v-mx_se/mainboard.c @@ -40,7 +40,7 @@ int add_mainboard_resources(struct lb_memory *mem) #if CONFIG_HAVE_ACPI_RESUME == 1 lb_add_memory_range(mem, LB_MEM_RESERVED, - CONFIG_RAMBASE, ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_RAMBASE)); + CONFIG_RAMBASE, ((CONFIG_RAMTOP) - CONFIG_RAMBASE)); lb_add_memory_range(mem, LB_MEM_RESERVED, CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); #endif diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb index 2c18f9da2a..97a8a4ccc2 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb +++ b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb @@ -105,7 +105,7 @@ uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -135,7 +135,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot diff --git a/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c b/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c index 6fb051e7c8..90546b45a2 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c @@ -89,7 +89,7 @@ static void post_code(uint8_t value) { void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/gigabyte/m57sli/Options.lb b/src/mainboard/gigabyte/m57sli/Options.lb index 73b46894f5..0a0d29246a 100644 --- a/src/mainboard/gigabyte/m57sli/Options.lb +++ b/src/mainboard/gigabyte/m57sli/Options.lb @@ -105,7 +105,7 @@ uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -136,7 +136,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Set-up automatic fan control diff --git a/src/mainboard/gigabyte/m57sli/apc_auto.c b/src/mainboard/gigabyte/m57sli/apc_auto.c index d0730b935a..176e6b41ad 100644 --- a/src/mainboard/gigabyte/m57sli/apc_auto.c +++ b/src/mainboard/gigabyte/m57sli/apc_auto.c @@ -87,7 +87,7 @@ static void post_code(uint8_t value) { void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/hp/dl145_g3/Options.lb b/src/mainboard/hp/dl145_g3/Options.lb index 2a598c35ea..5ae7fb27c5 100644 --- a/src/mainboard/hp/dl145_g3/Options.lb +++ b/src/mainboard/hp/dl145_g3/Options.lb @@ -102,7 +102,7 @@ uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_USE_PRINTK_IN_CAR @@ -121,7 +121,7 @@ default CONFIG_ROM_SIZE=524288 default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot diff --git a/src/mainboard/intel/truxton/Options.lb b/src/mainboard/intel/truxton/Options.lb index 3815885005..dab3f45b77 100644 --- a/src/mainboard/intel/truxton/Options.lb +++ b/src/mainboard/intel/truxton/Options.lb @@ -35,7 +35,7 @@ uses CONFIG_ROM_SECTION_SIZE uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD uses CONFIG_COMPRESSED_PAYLOAD_LZMA -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_ROMBASE uses CONFIG_XIP_ROM_SIZE uses CONFIG_XIP_ROM_BASE @@ -157,9 +157,9 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_RAMBASE=0x00100000 ## -## in order to have coreboot running at 0x100000, TOPK has to be set +## in order to have coreboot running at 0x100000, RAMTOP has to be set ## -default CONFIG_LB_MEM_TOPK = 2*1024*1024 +default CONFIG_RAMTOP = 2*1024*1024 ## ## Load the payload from the ROM diff --git a/src/mainboard/iwill/dk8_htx/Options.lb b/src/mainboard/iwill/dk8_htx/Options.lb index 1e5484a81a..f35afb4f81 100644 --- a/src/mainboard/iwill/dk8_htx/Options.lb +++ b/src/mainboard/iwill/dk8_htx/Options.lb @@ -80,7 +80,7 @@ uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -109,7 +109,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE=0x02000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot diff --git a/src/mainboard/msi/ms7135/Options.lb b/src/mainboard/msi/ms7135/Options.lb index 2d09cd026b..23377342d0 100644 --- a/src/mainboard/msi/ms7135/Options.lb +++ b/src/mainboard/msi/ms7135/Options.lb @@ -99,9 +99,6 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_LB_MEM_TOPK - - ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. ## ---> 512 Kbytes default CONFIG_ROM_SIZE=(512*1024) diff --git a/src/mainboard/msi/ms7260/Options.lb b/src/mainboard/msi/ms7260/Options.lb index 8e52def02a..54b62c1d01 100644 --- a/src/mainboard/msi/ms7260/Options.lb +++ b/src/mainboard/msi/ms7260/Options.lb @@ -91,7 +91,7 @@ uses CONFIG_ENABLE_APIC_EXT_ID uses CONFIG_APIC_ID_OFFSET uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR uses CONFIG_MEM_TRAIN_SEQ uses CONFIG_WAIT_BEFORE_CPUS_INIT @@ -100,7 +100,7 @@ uses CONFIG_USE_PRINTK_IN_CAR default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE = 4 * 1024 -default CONFIG_LB_MEM_TOPK = 2048 # 1MB more for pgtbl. +default CONFIG_RAMTOP = 2048*1024 # 1MB more for pgtbl. default CONFIG_HAVE_FALLBACK_BOOT = 1 default CONFIG_HAVE_FAILOVER_BOOT = 1 default CONFIG_HAVE_HARD_RESET = 1 diff --git a/src/mainboard/msi/ms7260/apc_auto.c b/src/mainboard/msi/ms7260/apc_auto.c index 880952b267..6f01fad1f8 100644 --- a/src/mainboard/msi/ms7260/apc_auto.c +++ b/src/mainboard/msi/ms7260/apc_auto.c @@ -63,7 +63,7 @@ void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in CACHE */ - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK << 10) - + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); /* in RAM */ struct node_core_id id; diff --git a/src/mainboard/msi/ms9185/Options.lb b/src/mainboard/msi/ms9185/Options.lb index 41bbc995aa..d3423f59e1 100644 --- a/src/mainboard/msi/ms9185/Options.lb +++ b/src/mainboard/msi/ms9185/Options.lb @@ -101,7 +101,7 @@ uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_USE_PRINTK_IN_CAR ### @@ -118,7 +118,7 @@ default CONFIG_ROM_SIZE=524288 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot diff --git a/src/mainboard/nvidia/l1_2pvv/Options.lb b/src/mainboard/nvidia/l1_2pvv/Options.lb index a3d8f8e3ee..b7b445af36 100644 --- a/src/mainboard/nvidia/l1_2pvv/Options.lb +++ b/src/mainboard/nvidia/l1_2pvv/Options.lb @@ -103,7 +103,7 @@ uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -133,7 +133,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot diff --git a/src/mainboard/nvidia/l1_2pvv/apc_auto.c b/src/mainboard/nvidia/l1_2pvv/apc_auto.c index 525e940776..7528b84ed4 100644 --- a/src/mainboard/nvidia/l1_2pvv/apc_auto.c +++ b/src/mainboard/nvidia/l1_2pvv/apc_auto.c @@ -87,7 +87,7 @@ static void post_code(uint8_t value) { void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/supermicro/h8dme/Options.lb b/src/mainboard/supermicro/h8dme/Options.lb index 9f7095c43c..5a361350bc 100644 --- a/src/mainboard/supermicro/h8dme/Options.lb +++ b/src/mainboard/supermicro/h8dme/Options.lb @@ -104,7 +104,7 @@ uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -137,7 +137,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot diff --git a/src/mainboard/supermicro/h8dme/apc_auto.c b/src/mainboard/supermicro/h8dme/apc_auto.c index 442945e9f2..f4bedfe0f0 100644 --- a/src/mainboard/supermicro/h8dme/apc_auto.c +++ b/src/mainboard/supermicro/h8dme/apc_auto.c @@ -95,7 +95,7 @@ static inline unsigned get_nodes(void) void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/supermicro/h8dmr/Options.lb b/src/mainboard/supermicro/h8dmr/Options.lb index f95c63c4ba..5e457d03aa 100644 --- a/src/mainboard/supermicro/h8dmr/Options.lb +++ b/src/mainboard/supermicro/h8dmr/Options.lb @@ -102,7 +102,7 @@ uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -130,7 +130,7 @@ default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot diff --git a/src/mainboard/supermicro/h8dmr/apc_auto.c b/src/mainboard/supermicro/h8dmr/apc_auto.c index 442945e9f2..f4bedfe0f0 100644 --- a/src/mainboard/supermicro/h8dmr/apc_auto.c +++ b/src/mainboard/supermicro/h8dmr/apc_auto.c @@ -95,7 +95,7 @@ static inline unsigned get_nodes(void) void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/supermicro/h8dmr_fam10/Options.lb b/src/mainboard/supermicro/h8dmr_fam10/Options.lb index 2ad708a813..1342e4381a 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/Options.lb +++ b/src/mainboard/supermicro/h8dmr_fam10/Options.lb @@ -99,7 +99,7 @@ uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_UNCOMPRESSED @@ -132,7 +132,7 @@ default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE=0x02000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=16384 +default CONFIG_RAMTOP=16384*1024 ## ## Build code for the fallback boot diff --git a/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c b/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c index 099b6abd17..f55b80f826 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c +++ b/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c @@ -95,7 +95,7 @@ static inline unsigned get_nodes(void) void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/tyan/s2885/Options.lb b/src/mainboard/tyan/s2885/Options.lb index df76f5c93c..fc43fc834d 100644 --- a/src/mainboard/tyan/s2885/Options.lb +++ b/src/mainboard/tyan/s2885/Options.lb @@ -68,8 +68,6 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_LB_MEM_TOPK - ### ### Build options ### diff --git a/src/mainboard/tyan/s2891/Options.lb b/src/mainboard/tyan/s2891/Options.lb index 08a1a081f1..63c5f935da 100644 --- a/src/mainboard/tyan/s2891/Options.lb +++ b/src/mainboard/tyan/s2891/Options.lb @@ -77,8 +77,6 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_LB_MEM_TOPK - ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. default CONFIG_ROM_SIZE=512*1024 diff --git a/src/mainboard/tyan/s2892/Options.lb b/src/mainboard/tyan/s2892/Options.lb index 4ec42e5932..89a897bf96 100644 --- a/src/mainboard/tyan/s2892/Options.lb +++ b/src/mainboard/tyan/s2892/Options.lb @@ -71,8 +71,6 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_LB_MEM_TOPK - ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. default CONFIG_ROM_SIZE=1024*1024 diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb index de9e136f2d..864fc30dc3 100644 --- a/src/mainboard/tyan/s2895/Options.lb +++ b/src/mainboard/tyan/s2895/Options.lb @@ -80,7 +80,7 @@ uses CONFIG_HT_CHAIN_END_UNITID_BASE uses CONFIG_SB_HT_CHAIN_ON_BUS0 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. default CONFIG_ROM_SIZE=1024*1024 @@ -95,7 +95,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot diff --git a/src/mainboard/tyan/s2912/Options.lb b/src/mainboard/tyan/s2912/Options.lb index 439c6cf3eb..a8de386fef 100644 --- a/src/mainboard/tyan/s2912/Options.lb +++ b/src/mainboard/tyan/s2912/Options.lb @@ -103,7 +103,7 @@ uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_AP_CODE_IN_CAR @@ -133,7 +133,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=2048 +default CONFIG_RAMTOP=2048*1024 ## ## Build code for the fallback boot diff --git a/src/mainboard/tyan/s2912/apc_auto.c b/src/mainboard/tyan/s2912/apc_auto.c index 8985b7affd..2600dd3b6b 100644 --- a/src/mainboard/tyan/s2912/apc_auto.c +++ b/src/mainboard/tyan/s2912/apc_auto.c @@ -76,7 +76,7 @@ void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/tyan/s2912_fam10/Options.lb b/src/mainboard/tyan/s2912_fam10/Options.lb index 61c647cb86..29e4f136e7 100644 --- a/src/mainboard/tyan/s2912_fam10/Options.lb +++ b/src/mainboard/tyan/s2912_fam10/Options.lb @@ -101,7 +101,7 @@ uses CONFIG_LIFT_BSP_APIC_ID uses CONFIG_PCI_64BIT_PREF_MEM -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_PCI_BUS_SEGN_BITS @@ -135,7 +135,7 @@ default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE default CONFIG_FAILOVER_SIZE=0x01000 #more 1M for pgtbl -default CONFIG_LB_MEM_TOPK=16384 +default CONFIG_RAMTOP=16384*1024 ## ## Build code for the fallback boot diff --git a/src/mainboard/tyan/s2912_fam10/apc_auto.c b/src/mainboard/tyan/s2912_fam10/apc_auto.c index 8985b7affd..2600dd3b6b 100644 --- a/src/mainboard/tyan/s2912_fam10/apc_auto.c +++ b/src/mainboard/tyan/s2912_fam10/apc_auto.c @@ -76,7 +76,7 @@ void hardwaremain(int ret_addr) { struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE - struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM + struct sys_info *sysinfox = ((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct node_core_id id; diff --git a/src/mainboard/via/epia-n/Options.lb b/src/mainboard/via/epia-n/Options.lb index e9dfad17cd..7d229c5302 100644 --- a/src/mainboard/via/epia-n/Options.lb +++ b/src/mainboard/via/epia-n/Options.lb @@ -34,7 +34,7 @@ uses CONFIG_MAINBOARD_VENDOR uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION uses CONFIG_ARCH -uses CONFIG_LB_MEM_TOPK +uses CONFIG_RAMTOP uses CONFIG_FALLBACK_SIZE uses CONFIG_STACK_SIZE uses CONFIG_HEAP_SIZE @@ -73,7 +73,7 @@ uses CONFIG_EPIA_VT8237R_INIT uses CONFIG_HAVE_MAINBOARD_RESOURCES default CONFIG_EPIA_VT8237R_INIT = 1 -#default CONFIG_LB_MEM_TOPK = 4 * 1024 +#default CONFIG_RAMTOP = 4 * 1024*1024 default CONFIG_ROM_SIZE = 512 * 1024 default CONFIG_COMPRESS = 1 default CONFIG_IOAPIC = 1 -- cgit v1.2.3