From 1c8cd59f3c9248f0954a5cf215dc3652ccfc8da5 Mon Sep 17 00:00:00 2001 From: "arch import user (historical)" Date: Wed, 6 Jul 2005 17:15:54 +0000 Subject: Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-38 Creator: Li-Ta Lo emulator update x96emu update from Paulo git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/arima/hdama/Config.lb | 63 +++++++++---------- src/mainboard/arima/hdama/Options.lb | 6 -- src/mainboard/ibm/e325/auto.c | 9 +-- src/mainboard/ibm/e325/failover.c | 5 +- src/mainboard/via/epia/Config.lb | 117 +++++++++++++++++------------------ src/mainboard/via/epia/Options.lb | 19 ------ src/mainboard/via/epia/auto.c | 24 +++++-- 7 files changed, 108 insertions(+), 135 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb index a9df17bcdf..5d065fa4cf 100644 --- a/src/mainboard/arima/hdama/Config.lb +++ b/src/mainboard/arima/hdama/Config.lb @@ -129,61 +129,48 @@ config chip.h # config for arima/hdama chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on - chip cpu/amd/socket_940 - device apic 0 on end - end - chip cpu/amd/socket_940 - device apic 1 on end - end - end device pci_domain 0 on chip northbridge/amd/amdk8 device pci 18.0 on # northbridge # devices on link 0, link 0 == LDT 0 chip southbridge/amd/amd8131 # the on/off keyword is mandatory - device pci 0.0 on end # PCIX bridge - device pci 0.1 on end # IOAPIC - device pci 1.0 on end # PCIX bridge - device pci 1.1 on end # IOAPIC + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end end chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent of the next one + # this "device pci 0.0" is the parent the next one # PCI bridge device pci 0.0 on - device pci 0.0 on end # USB0 - device pci 0.1 on end # USB1 - device pci 0.2 off end # USB 2.0 - device pci 1.0 off end # LAN - chip drivers/pci/onboard - device pci 6.0 on end # ATI Rage XL - register "rom_address" = "0xfff80000" - end + device pci 0.0 on end + device pci 0.1 on end + device pci 0.2 off end + device pci 1.0 off end end - # LPC bridge device pci 1.0 on chip superio/NSC/pc87360 - device pnp 2e.0 off # Floppy + device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end - device pnp 2e.1 off # Parallel Port + device pnp 2e.1 off # Parallel Port io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 2e.2 off # Com 2 + device pnp 2e.2 off # Com 2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.3 on # Com 1 + device pnp 2e.3 on # Com 1 io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.4 off end # SWC device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard + device pnp 2e.6 on # Keyboard io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 @@ -194,9 +181,9 @@ chip northbridge/amd/amdk8/root_complex device pnp 2e.a off end # WDT end end - device pci 1.1 on end # IDE - device pci 1.2 on end # SMBus 2.0 - device pci 1.3 on # System Management + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on chip drivers/generic/generic #phillips pca9545 smbus mux device i2c 70 on @@ -234,19 +221,19 @@ chip northbridge/amd/amdk8/root_complex device i2c 57 on end end end - device pci 1.5 off end # AC97 Audio - device pci 1.6 on end # AC97 Modem + device pci 1.5 off end + device pci 1.6 on end register "ide0_enable" = "1" register "ide1_enable" = "1" end - end # device pci 18.0 + end # device pci 18.0 device pci 18.0 on end # LDT1 device pci 18.0 on end # LDT2 device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end - end # chip northbridge/amd/amdk8 + end chip northbridge/amd/amdk8 device pci 19.0 on end device pci 19.0 on end @@ -255,6 +242,14 @@ chip northbridge/amd/amdk8/root_complex device pci 19.2 on end device pci 19.3 on end end + end + device apic_cluster 0 on + chip cpu/amd/socket_940 + device apic 0 on end + end + chip cpu/amd/socket_940 + device apic 1 on end + end end end diff --git a/src/mainboard/arima/hdama/Options.lb b/src/mainboard/arima/hdama/Options.lb index 1972c39fe4..091f792e3b 100644 --- a/src/mainboard/arima/hdama/Options.lb +++ b/src/mainboard/arima/hdama/Options.lb @@ -50,8 +50,6 @@ uses CROSS_COMPILE uses CC uses HOSTCC uses OBJCOPY -uses CONFIG_CONSOLE_VGA -uses CONFIG_PCI_ROM_RUN ### ### Build options @@ -121,10 +119,6 @@ default CONFIG_MAX_PHYSICAL_CPUS=2 ## default CONFIG_IOAPIC=1 -#VGA -default CONFIG_CONSOLE_VGA=1 -default CONFIG_PCI_ROM_RUN=1 - ## ## Clean up the motherboard id strings ## diff --git a/src/mainboard/ibm/e325/auto.c b/src/mainboard/ibm/e325/auto.c index b1c9e772d5..dbbcbf597b 100644 --- a/src/mainboard/ibm/e325/auto.c +++ b/src/mainboard/ibm/e325/auto.c @@ -158,21 +158,16 @@ static void main(unsigned long bist) }; int needs_reset; - unsigned nodeid; - if (bist == 0) { /* Skip this if there was a built in self test failure */ amd_early_mtrr_init(); enable_lapic(); init_timer(); - - nodeid = lapicid() & 0xf; - /* Has this cpu already booted? */ - if (cpu_init_detected(nodeid)) { + if (cpu_init_detected()) { asm volatile ("jmp __cpu_reset"); } - distinguish_cpu_resets(nodeid); + distinguish_cpu_resets(); if (!boot_cpu()) { stop_this_cpu(); } diff --git a/src/mainboard/ibm/e325/failover.c b/src/mainboard/ibm/e325/failover.c index ed5ce32d81..e351cae83d 100644 --- a/src/mainboard/ibm/e325/failover.c +++ b/src/mainboard/ibm/e325/failover.c @@ -13,14 +13,11 @@ static unsigned long main(unsigned long bist) { - unsigned nodeid; /* Make cerain my local apic is useable */ enable_lapic(); - nodeid = lapicid() & 0xf; - /* Is this a cpu only reset? */ - if (cpu_init_detected(nodeid)) { + if (cpu_init_detected()) { if (last_boot_normal()) { goto normal_image; } else { diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb index 96c543a1ec..448d86fb09 100644 --- a/src/mainboard/via/epia/Config.lb +++ b/src/mainboard/via/epia/Config.lb @@ -125,64 +125,61 @@ dir /pc80 config chip.h chip northbridge/via/vt8601 - device pci_domain 0 on - device pci 0.0 on end # Northbridge - device pci 0.1 on # AGP bridge - # chip drivers/pci/onboard # Integrated VGA - # device pci 0.0 on end - # register "rom_adress" = "0xfff80000" - # end - end - chip southbridge/via/vt8231 - register "enable_native_ide" = "0" - register "enable_com_ports" = "1" - register "enable_keyboard" = "0" - device pci 11.0 on # Southbrdge - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - register "com1" = "{1}" - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - end - end - device pci 11.1 on end # Ide - device pci 11.2 off end # Usb port 0-1 - device pci 11.3 off end # Usb port 2-3 - device pci 11.4 off end # ACPI - device pci 11.5 off end # AC97 Audio - device pci 11.6 on end # AC97 Modem - device pci 12.0 on end # Ethernet - end - end - - chip cpu/via/model_centaur - end + device pci_domain 0 on + device pci 0.0 on + chip southbridge/via/vt8231 + register "enable_usb" = "0" + register "enable_native_ide" = "0" + register "enable_com_ports" = "1" + register "enable_keyboard" = "0" + register "enable_nvram" = "1" + device pci 11.0 on # Southbridge + device pci 11.1 on end # Ide + device pci 11.2 off end # Usb + device pci 11.3 off end # Usb + device pci 11.4 off end # ACPI + device pci 11.5 off end # Audio + device pci 11.6 on # Com + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + end + register "com1" = "{1}" + end + end + device pci 12.0 on end # Ethernet + end + end + end + end + chip cpu/via/model_centaur + end end diff --git a/src/mainboard/via/epia/Options.lb b/src/mainboard/via/epia/Options.lb index 259acfbc24..d8d3490dd0 100644 --- a/src/mainboard/via/epia/Options.lb +++ b/src/mainboard/via/epia/Options.lb @@ -1,10 +1,3 @@ -uses MAXIMUM_CONSOLE_LOGLEVEL -uses DEFAULT_CONSOLE_LOGLEVEL -uses CONFIG_CONSOLE_SERIAL8250 -uses TTYS0_BAUD -uses TTYS0_BASE -uses TTYS0_LCS -uses CONFIG_CHIP_NAME uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE @@ -47,18 +40,6 @@ uses MAXIMUM_CONSOLE_LOGLEVEL uses DEFAULT_CONSOLE_LOGLEVEL uses MAXIMUM_CONSOLE_LOGLEVEL -default CONFIG_CONSOLE_SERIAL8250=1 -## Select the serial console baud rate -default TTYS0_BAUD=19200 - -# Select the serial console base port -default TTYS0_BASE=0x3f8 - -# Select the serial protocol -# This defaults to 8 data bits, 1 stop bit, and no parity -default TTYS0_LCS=0x3 - -default CONFIG_CHIP_NAME=1 ## ROM_SIZE is the size of boot ROM that this board will use. default ROM_SIZE = 256*1024 diff --git a/src/mainboard/via/epia/auto.c b/src/mainboard/via/epia/auto.c index 9e12f52a7c..6c8ea903ee 100644 --- a/src/mainboard/via/epia/auto.c +++ b/src/mainboard/via/epia/auto.c @@ -2,6 +2,9 @@ #include #include +#if 0 +#include +#endif #include #include #include @@ -18,7 +21,7 @@ void udelay(int usecs) { int i; - for (i = 0; i < usecs; i++) + for(i = 0; i < usecs; i++) outb(i&0xff, 0x80); } @@ -27,8 +30,18 @@ void udelay(int usecs) #include "debug.c" #include "southbridge/via/vt8231/vt8231_early_smbus.c" + + #include "southbridge/via/vt8231/vt8231_early_serial.c" +static void memreset_setup(void) +{ +} +/* + static void memreset(int controllers, const struct mem_controller *ctrl) + { + } +*/ static inline int spd_read_byte(unsigned device, unsigned address) { unsigned char c; @@ -36,6 +49,8 @@ static inline int spd_read_byte(unsigned device, unsigned address) return c; } + + #include "northbridge/via/vt8601/raminit.c" /* #include "sdram/generic_sdram.c" @@ -51,7 +66,6 @@ static void enable_mainboard_devices(void) if (dev == PCI_DEV_INVALID) { die("Southbridge not found!!!\n"); } - pci_write_config8(dev, 0x50, 7); pci_write_config8(dev, 0x51, 0xff); #if 0 @@ -73,9 +87,9 @@ static void enable_mainboard_devices(void) static void enable_shadow_ram(void) { - device_t dev = 0; + device_t dev = 0; /* no need to look up 0:0.0 */ unsigned char shadowreg; - + /* dev 0 for southbridge */ shadowreg = pci_read_config8(dev, 0x63); /* 0xf0000-0xfffff */ shadowreg |= 0x30; @@ -99,8 +113,8 @@ static void main(unsigned long bist) enable_mainboard_devices(); enable_smbus(); enable_shadow_ram(); - /* + memreset_setup(); this is way more generic than we need. sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); */ -- cgit v1.2.3