From 399fcdd40d24e7f6fed80e5e1493c900be2b3772 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 23 Feb 2012 18:42:55 +0200 Subject: AMD southbridge: remove sp5100 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Southbridge SP5100 support was compiled with SB700 code, but static device info structure would use sp5100/chip.h. To solve this drop support for separate chip sp5100 and adjust the relevant Kconfig options. Removes chip directory: src/southbridge/amd/sp5100/ Rename Kconfig option from: SOUTHBRIDGE_AMD_SP5100 to: SOUTHBRIDGE_AMD_SUBTYPE_SP5100 Change-Id: I873c6ad3624ee69165da6ab7287dfb7e006ee8e8 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/679 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao Reviewed-by: Marc Jones --- src/mainboard/supermicro/h8scm_fam10/Kconfig | 4 ++-- src/mainboard/supermicro/h8scm_fam10/devicetree.cb | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mainboard') diff --git a/src/mainboard/supermicro/h8scm_fam10/Kconfig b/src/mainboard/supermicro/h8scm_fam10/Kconfig index cbd3119544..844763e211 100755 --- a/src/mainboard/supermicro/h8scm_fam10/Kconfig +++ b/src/mainboard/supermicro/h8scm_fam10/Kconfig @@ -8,14 +8,14 @@ config BOARD_SPECIFIC_OPTIONS # dummy select DIMM_REGISTERED select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_AMD_SR5650 - select SOUTHBRIDGE_AMD_SP5100 + select SOUTHBRIDGE_AMD_SB700 + select SOUTHBRIDGE_AMD_SUBTYPE_SP5100 select SUPERIO_WINBOND_W83627HF select SUPERIO_NUVOTON_WPCM450 select HAVE_BUS_CONFIG select HAVE_OPTION_TABLE select GENERATE_PIRQ_TABLE select GENERATE_MP_TABLE - select HAVE_HARD_RESET select SB_HT_CHAIN_UNITID_OFFSET_ONLY select LIFT_BSP_APIC_ID select SERIAL_CPU_INIT diff --git a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb index c6ccecb171..9aa4406faf 100644 --- a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb @@ -36,7 +36,7 @@ chip northbridge/amd/amdfam10/root_complex register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1 register "port_enable" = "0x1ffc" end - chip southbridge/amd/sp5100 # it is under NB/SB Link, but on the same pri bus + chip southbridge/amd/sb700 # (model:sp5100) it is under NB/SB Link, but on the same pri bus device pci 11.0 on end # SATA device pci 12.0 on end # USB device pci 12.1 on end # USB @@ -92,7 +92,7 @@ chip northbridge/amd/amdfam10/root_complex device pci 14.4 on end # PCI 0x4384 device pci 14.5 on end # USB 2 register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sp5100 + end #southbridge/amd/sb700 end # device pci 18.0 device pci 18.1 on end device pci 18.2 on end -- cgit v1.2.3